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The cores are designed by the method of spatial SDF mapping into the hardware, which provides the minimized hardware volume at the cost of slowdown of the algorithm by<mml:math xmlns:mml=\"http:\/\/www.w3.org\/1998\/Math\/MathML\" id=\"M2\"><mml:mrow><mml:mi>r<\/mml:mi><\/mml:mrow><\/mml:math>times. Their clock frequency is equal to the data sampling frequency. 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