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By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding schedule without utilizing additional hardware resources. High-level synthesis compilation is used to design and develop the architecture on the FPGA hardware platform. To validate this architecture, an<jats:italic> IEEE 802.11n<\/jats:italic> compliant 608\u2009Mb\/s decoder is implemented on the<jats:italic> Xilinx Kintex-7<\/jats:italic> FPGA using the<jats:italic> LabVIEW FPGA Compiler<\/jats:italic> in the<jats:italic> LabVIEW Communication System Design Suite<\/jats:italic>. Architecture scalability was leveraged to accomplish a 2.48\u2009Gb\/s decoder on a single<jats:italic> Xilinx Kintex-7<\/jats:italic> FPGA. Further, we present rapidly prototyped experimentation of an<jats:italic> IEEE 802.16<\/jats:italic> compliant hybrid automatic repeat request system based on the efficient decoder architecture developed. In spite of the<jats:italic> mixed<\/jats:italic> nature of data processing\u2014digital signal processing and finite-state machines\u2014<jats:italic>LabVIEW FPGA Compiler<\/jats:italic> significantly reduced time to explore the system parameter space and to optimize in terms of error performance and resource utilization. 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