{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,20]],"date-time":"2026-03-20T15:40:09Z","timestamp":1774021209967,"version":"3.50.1"},"reference-count":16,"publisher":"Wiley","license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["International Journal of Reconfigurable Computing"],"published-print":{"date-parts":[[2018]]},"abstract":"<jats:p>The mathematical model for designing a complex digital system is a finite state machine (FSM). Applications such as digital signal processing (DSP) and built-in self-test (BIST) require specific operations to be performed only in the particular instances. Hence, the optimal synthesis of such systems requires a reconfigurable FSM. The objective of this paper is to create a framework for a reconfigurable FSM with input multiplexing and state-based input selection (Reconfigurable FSMIM-S) architecture. The Reconfigurable FSMIM-S architecture is constructed by combining the conventional FSMIM-S architecture and an optimized multiplexer bank (which defines the mode of operation). For this, the descriptions of a set of FSMs are taken for a particular application. The problem of obtaining the required optimized multiplexer bank is transformed into a weighted bipartite graph matching problem where the objective is to iteratively match the description of FSMs in the set with minimal cost. As a solution, an iterative greedy heuristic based Hungarian algorithm is proposed. The experimental results from MCNC FSM benchmarks demonstrate a significant speed improvement by 30.43% as compared with variation-based reconfigurable multiplexer bank (VRMUX) and by 9.14% in comparison with combination-based reconfigurable multiplexer bank (CRMUX) during field programmable gate array (FPGA) implementation.<\/jats:p>","DOI":"10.1155\/2018\/6831901","type":"journal-article","created":{"date-parts":[[2018,1,10]],"date-time":"2018-01-10T18:42:44Z","timestamp":1515609764000},"page":"1-15","source":"Crossref","is-referenced-by-count":12,"title":["FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method"],"prefix":"10.1155","volume":"2018","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3920-0304","authenticated-orcid":true,"given":"Nitish","family":"Das","sequence":"first","affiliation":[{"name":"Department of ECE, SRM University, Kattankulathur, Chennai 603203, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5612-3312","authenticated-orcid":true,"given":"P. Aruna","family":"Priya","sequence":"additional","affiliation":[{"name":"Department of ECE, SRM University, Kattankulathur, Chennai 603203, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","reference":[{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/2000832.2000835"},{"key":"2","volume":"45","year":"2016"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2014.12.001"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2017.01.021"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1049\/el:20046007"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2406859"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126615501017"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1016\/j.dam.2015.01.008"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1016\/j.parco.2016.05.012"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1080\/02522667.2014.926711"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1007\/s10479-016-2118-3"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1007\/s12597-013-0158-x"},{"key":"19","doi-asserted-by":"publisher","DOI":"10.1134\/S1064230715030090"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-45378-1_64"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2015.0038"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2016.08.001"}],"container-title":["International Journal of Reconfigurable Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/journals\/ijrc\/2018\/6831901.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/ijrc\/2018\/6831901.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/ijrc\/2018\/6831901.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,1,10]],"date-time":"2018-01-10T18:42:44Z","timestamp":1515609764000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.hindawi.com\/journals\/ijrc\/2018\/6831901\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"references-count":16,"alternative-id":["6831901","6831901"],"URL":"https:\/\/doi.org\/10.1155\/2018\/6831901","relation":{},"ISSN":["1687-7195","1687-7209"],"issn-type":[{"value":"1687-7195","type":"print"},{"value":"1687-7209","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018]]}}}