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By using a newly added digital filter between the phase detector and the controller, the phase difference pulses from the phase detector are counted and processed, before being transmitted to the controller for adjusting the phase of the output clock. The design is completed by using FPGA chip and VHDL hardware description language and performs the simulation verification on Quartus II. The results show that the improved system performs the accurate extraction of bit synchronized clock, reduces the phase jitter problem, improves the system running efficiency and the ability of anti-interference, and guarantees the synchronization performance of the digital communication system.<\/jats:p>","DOI":"10.1155\/2018\/8024168","type":"journal-article","created":{"date-parts":[[2018,7,3]],"date-time":"2018-07-03T00:45:32Z","timestamp":1530578732000},"page":"1-8","source":"Crossref","is-referenced-by-count":0,"title":["Improved Design of Bit Synchronization Clock Extraction in Digital Communication System"],"prefix":"10.1155","volume":"2018","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1628-0014","authenticated-orcid":true,"given":"Huimin","family":"Duan","sequence":"first","affiliation":[{"name":"Department of Electronic and Electrical Engineering, Hefei University, Hefei, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hui","family":"Huang","sequence":"additional","affiliation":[{"name":"Department of Electronic and Electrical Engineering, Hefei University, Hefei, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cuihua","family":"Li","sequence":"additional","affiliation":[{"name":"Department of Electronic and Electrical Engineering, Hefei University, Hefei, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","reference":[{"key":"1","doi-asserted-by":"publisher","DOI":"10.1007\/s11431-015-5974-1"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1007\/s11128-015-1093-y"},{"year":"2016","key":"3"},{"issue":"4","key":"4","first-page":"132","volume":"39","year":"2016","journal-title":"Modern Electronics Technique"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1002\/cta.2103"},{"issue":"4","key":"6","first-page":"36","year":"2017","journal-title":"Electronic Technology"},{"issue":"10","key":"7","first-page":"2397","volume":"39","year":"2017","journal-title":"Journal of Electronics and Information Technology"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/LSP.2016.2542291"},{"issue":"7","key":"9","first-page":"102","volume":"29","year":"2016","journal-title":"Electronic Science and Technology"},{"issue":"4","key":"10","first-page":"990","volume":"48","year":"2017","journal-title":"Journal of Central South University (Science and Technology)"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2017.06.004"},{"issue":"12","key":"12","first-page":"55","volume":"43","year":"2017","journal-title":"Measurement Control Technology and Instruments"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-016-5604-2"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1016\/j.arcontrol.2016.08.003"},{"key":"15","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1080\/17445760.2016.1156109","volume":"32","year":"2017","journal-title":"International Journal of Parallel, Emergent and Distributed Systems"},{"issue":"20","key":"16","first-page":"171","volume":"32","year":"2017","journal-title":"Transactions of China Electrotechnical Society"},{"issue":"2","key":"17","first-page":"172","volume":"30","year":"2015","journal-title":"Transactions of China Electrotechnical Society"},{"year":"2013","series-title":"translated by Y. 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