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To achieve real-time path-planning performance, a hardware accelerator\u2019s architecture called A<mml:math xmlns:mml=\"http:\/\/www.w3.org\/1998\/Math\/MathML\" id=\"M3\"><mml:msup><mml:mrow\/><mml:mrow><mml:mi>\u2217<\/mml:mi><\/mml:mrow><\/mml:msup><\/mml:math> accelerator has been designed and implemented in field programmable gate array (FPGA). The specially designed 8-port cache and OPEN list array are introduced to tackle the calculation bottleneck. The system-on-a-chip (SOC) design is implemented in Xilinx Kintex-7 FPGA to evaluate A<mml:math xmlns:mml=\"http:\/\/www.w3.org\/1998\/Math\/MathML\" id=\"M4\"><mml:msup><mml:mrow\/><mml:mrow><mml:mi>\u2217<\/mml:mi><\/mml:mrow><\/mml:msup><\/mml:math> accelerator. Experiments show that the hardware accelerator achieves 37\u201375 times performance enhancement relative to software implementation. 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