{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T13:18:33Z","timestamp":1753881513617,"version":"3.41.2"},"reference-count":16,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2021,5,25]],"date-time":"2021-05-25T00:00:00Z","timestamp":1621900800000},"content-version":"vor","delay-in-days":144,"URL":"http:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"National Key R&D Program of China","award":["2020YFB0906000","2020YFB0906001"],"award-info":[{"award-number":["2020YFB0906000","2020YFB0906001"]}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["Journal of Sensors"],"published-print":{"date-parts":[[2021,1]]},"abstract":"<jats:p>This paper introduces a small\u2010area, low\u2010power delta\u2010sigma DAC that can support power line carrier communication. In order to achieve the oversampling ratio of 128, a three\u2010stage cascaded half\u2010band filter is utilized. An optimized sturdy MASH <jats:italic>\u0394<\/jats:italic><jats:italic>\u03a3<\/jats:italic> modulator was used to avoid instability caused by high\u2010order shaping and reduce the area at the same time. The postanalog reconstruction includes a switched\u2010capacitor DAC (SC DAC) and a 4\u2010tap FIR\/IIR hybrid filter, which not only meets the requirements of low power but also promotes the out\u2010of\u2010band SNR. The final chip is fabricated in a 55\u2009nm CMOS process, occupies 0.08\u2009mm<jats:sup>2<\/jats:sup>, and consumes 1.5\u2009mW of analog power at 2.5\u2009V supply. The simulation results show that the dynamic range is 85.7\u2009dB, while the out\u2010of\u2010band SNR is 40.5\u2009dB.<\/jats:p>","DOI":"10.1155\/2021\/6630100","type":"journal-article","created":{"date-parts":[[2021,5,25]],"date-time":"2021-05-25T17:50:09Z","timestamp":1621965009000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A Small\u2010Area, Low\u2010Power Delta\u2010Sigma DAC Applied to a Power\u2010Specific Chip"],"prefix":"10.1155","volume":"2021","author":[{"given":"Peng","family":"Li","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei","family":"Xi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiangjun","family":"Zeng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaobo","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6873-9616","authenticated-orcid":false,"given":"Dandan","family":"Zheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2021,5,25]]},"reference":[{"volume-title":"CMOS VLSI design: a circuits and systems perspective","year":"2005","author":"Weste N. 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