{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,27]],"date-time":"2025-12-27T07:25:22Z","timestamp":1766820322694,"version":"3.40.5"},"reference-count":25,"publisher":"Wiley","license":[{"start":{"date-parts":[[2023,10,21]],"date-time":"2023-10-21T00:00:00Z","timestamp":1697846400000},"content-version":"unspecified","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"SIGER-USMBA"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Applied Computational Intelligence and Soft Computing"],"published-print":{"date-parts":[[2023,10,21]]},"abstract":"<jats:p>Ultra-reliable low-latency communications, URLLC, are designed for applications such as self-driving cars and telesurgery requiring a response in milliseconds and are very sensitive to transmission errors. To match the computational complexity of LDPC decoding algorithms to URLLC applications on IoT devices having very limited computational resources, this paper presents a new parallel and low-latency software implementation of the LDPC decoder. First, a decoding algorithm optimization and a compact data structure are proposed. Next, a parallel software implementation is performed on ARM multicore platforms in order to evaluate the latency of the proposed optimization. The synthesis results highlight a reduction in the memory size requirement by 50% and a three-time speedup in terms of processing time when compared to previous software decoder implementations. The reached decoding latency on the parallel processing platform is 150\u2009\u03bcs for 288\u2009bits with a bit error ratio of 3.410\u20139.<\/jats:p>","DOI":"10.1155\/2023\/5573438","type":"journal-article","created":{"date-parts":[[2023,10,21]],"date-time":"2023-10-21T17:50:06Z","timestamp":1697910606000},"page":"1-12","source":"Crossref","is-referenced-by-count":3,"title":["Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications"],"prefix":"10.1155","volume":"2023","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1952-7059","authenticated-orcid":true,"given":"Mhammed","family":"Benhayoun","sequence":"first","affiliation":[{"name":"University Sidi Mohammed Ben Abdellah, Faculty of Sciences and Technology, Laboratory of Intelligent Systems, Georesources and Renewable Energies, P.O. Box 2202, Fez, Morocco"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-9946-8964","authenticated-orcid":true,"given":"Mouhcine","family":"Razi","sequence":"additional","affiliation":[{"name":"University Sidi Mohammed Ben Abdellah, Faculty of Sciences and Technology, Laboratory of Intelligent Systems, Georesources and Renewable Energies, P.O. Box 2202, Fez, Morocco"}]},{"given":"Anas","family":"Mansouri","sequence":"additional","affiliation":[{"name":"University Sidi Mohammed Ben Abdellah, National School of Applied Sciences, Laboratory of Intelligent Systems, Georesources and Renewable Energies, Fez, Morocco"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1133-1887","authenticated-orcid":true,"given":"Ali","family":"Ahaitouf","sequence":"additional","affiliation":[{"name":"University Sidi Mohammed Ben Abdellah, Faculty of Sciences and Technology, Laboratory of Intelligent Systems, Georesources and Renewable Energies, P.O. Box 2202, Fez, Morocco"}]}],"member":"311","reference":[{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/tit.1962.1057683"},{"doi-asserted-by":"publisher","key":"2","DOI":"10.1049\/el:19961141"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/tit.1981.1056404"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1109\/18.910572"},{"year":"2022","author":"GPP","article-title":"3GPP release 38.913-h00 of URLLC requirement","key":"5"},{"issue":"4","key":"6","doi-asserted-by":"crossref","first-page":"642","DOI":"10.21629\/JSEE.2019.04.02","article-title":"Implementation of encoder and decoder for LDPC codes based on FPGA","volume":"30","author":"C. Kun","year":"2019","journal-title":"Journal of Systems Engineering and Electronics"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.3390\/electronics9010122"},{"key":"8","doi-asserted-by":"crossref","DOI":"10.1007\/978-981-33-4389-4_14","article-title":"FPGA implementation of scaled \u201cquasi-cyclic LDPC\u201d decoder using high-level synthesis","volume-title":"Proceedings of 1st International Conference on Mathematical Modeling and Computational Science","author":"S. A. Tamkeen","year":"2021"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/TVT.2022.3203802"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/les.2021.3052714"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1049\/iet-cds.2019.0160"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.3390\/electronics11213447"},{"author":"A. Kharin","first-page":"1","article-title":"LDPC decoder implementation on DSP+ARM platform with OpenCL","key":"13"},{"doi-asserted-by":"publisher","key":"14","DOI":"10.11591\/ijece.v11i6.pp4774-4784"},{"issue":"2","key":"15","article-title":"Iterative effect on LDPC code performance","volume":"1","author":"L. Mostari","year":"2012","journal-title":"Revue M\u00e9diterran\u00e9enne des T\u00e9l\u00e9communications"},{"doi-asserted-by":"publisher","key":"16","DOI":"10.1155\/2022\/1407788"},{"author":"J. Li","first-page":"1","article-title":"Decoding of quasi-cyclic LDPC codes with section-wise cyclic structure","key":"17"},{"doi-asserted-by":"publisher","key":"18","DOI":"10.1155\/2018\/5264724"},{"author":"A. Abotabl","first-page":"1","article-title":"Offset min-sum optimization for general decoding scheduling: a deep learning approach","key":"19"},{"key":"20","doi-asserted-by":"crossref","DOI":"10.1109\/ISTC49272.2021.9594227","article-title":"Neural-network-optimized degree-specific weights for LDPC minsum decoding","author":"L. Wang","year":"2021"},{"doi-asserted-by":"publisher","key":"21","DOI":"10.1109\/TCCN.2022.3212438"},{"doi-asserted-by":"publisher","key":"22","DOI":"10.3390\/e25020357"},{"doi-asserted-by":"publisher","key":"23","DOI":"10.1109\/access.2021.3112740"},{"doi-asserted-by":"publisher","key":"24","DOI":"10.1049\/cmu2.12361"},{"year":"2023","author":"Valgrind","article-title":"Valgrind documentation","key":"25"}],"container-title":["Applied Computational Intelligence and Soft Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/journals\/acisc\/2023\/5573438.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/acisc\/2023\/5573438.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/acisc\/2023\/5573438.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,21]],"date-time":"2023-10-21T17:50:13Z","timestamp":1697910613000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.hindawi.com\/journals\/acisc\/2023\/5573438\/"}},"subtitle":[],"editor":[{"given":"Kalapraveen","family":"Bagadi","sequence":"additional","affiliation":[]}],"short-title":[],"issued":{"date-parts":[[2023,10,21]]},"references-count":25,"alternative-id":["5573438","5573438"],"URL":"https:\/\/doi.org\/10.1155\/2023\/5573438","relation":{},"ISSN":["1687-9732","1687-9724"],"issn-type":[{"type":"electronic","value":"1687-9732"},{"type":"print","value":"1687-9724"}],"subject":[],"published":{"date-parts":[[2023,10,21]]}}}