{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T00:31:43Z","timestamp":1773793903579,"version":"3.50.1"},"reference-count":22,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T00:00:00Z","timestamp":1761264000000},"content-version":"vor","delay-in-days":296,"URL":"http:\/\/creativecommons.org\/licenses\/by\/4.0\/"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/doi.wiley.com\/10.1002\/tdm_license_1.1"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["Journal of Electrical and Computer Engineering"],"published-print":{"date-parts":[[2025,1]]},"abstract":"<jats:p>This paper presents a VLSI implementation of a high\u2010speed, area\u2010efficient, multiplierless address generation architecture for the WiMAX deinterleaver, conforming to the IEEE 802.16e standard. The primary motivation of this work is to reduce hardware complexity and delay by eliminating multipliers, which are traditionally used in address generation. The proposed architecture is designed for FPGA and ASIC platforms, emphasizing simplicity, reduced latency, and efficient hardware utilization. The design supports standard modulation schemes\u2014QPSK, 16\u2010QAM, and 64\u2010QAM\u2014with their respective code rates. Two key performance evaluations were conducted: Score 1, which refers to FPGA implementation on the Xilinx XC3S400, demonstrated a 13% increase in speed, and Score 2, based on ASIC analysis using 45\u2010nm CMOS technology, and achieved improvements of 17% in power delay product (PDP) and 22% in area delay product (ADP) over existing architectures. These results confirm the architecture\u2019s effectiveness for high\u2010speed, low\u2010power applications in modern communication systems.<\/jats:p>","DOI":"10.1155\/jece\/2638291","type":"journal-article","created":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T13:31:54Z","timestamp":1761312714000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["VLSI Implementation of High\u2010Speed and Area\u2010Efficient Multiplierless Address Generation Architecture for Deinterleaver in WiMAX Applications"],"prefix":"10.1155","volume":"2025","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0373-8724","authenticated-orcid":false,"given":"Vivek Karthick","family":"Perumal","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ramesh","family":"Jayabalan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eldho","family":"Paul","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6578-3956","authenticated-orcid":false,"given":"Dhanasekaran","family":"Selvaraj","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2025,10,24]]},"reference":[{"key":"e_1_2_11_1_2","first-page":"2230","article-title":"Matrix-Based Multi-Standard Interleavers","volume":"19","author":"Asghar M.","year":"2011","journal-title":"IEEE Transactions on Very Large Scale Integration Systems"},{"key":"e_1_2_11_2_2","first-page":"197","article-title":"A Survey of 802.11ax Technology","volume":"23","author":"Li J.","year":"2021","journal-title":"IEEE Communications Surveys and Tutorials"},{"key":"e_1_2_11_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/62.210638"},{"key":"e_1_2_11_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/98.788210"},{"key":"e_1_2_11_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/jsac.2004.839380"},{"key":"e_1_2_11_6_2","article-title":"High-Speed Physical Layer in the 5 GHz Band","author":"IEEE","year":"1999","journal-title":"IEEE Standard"},{"key":"e_1_2_11_7_2","article-title":"802.11 g, Higher Data Rate Extension in the 2.4 Ghz Band","author":"IEEE","year":"2003","journal-title":"IEEE Standard"},{"key":"e_1_2_11_8_2","unstructured":"IEEE 802.16e Air Interface for Fixed and Mobile Broadband Wireless Access Systems IEEE Standard 802 16e\u20132005."},{"key":"e_1_2_11_9_2","first-page":"492","article-title":"Efficient FPGA Implementation of an Address Generator for WiMAX Deinterleaver","volume":"60","author":"Upadhyaya B. K.","year":"2013","journal-title":"IEEE Transactions on Circuits and Systems II"},{"key":"e_1_2_11_10_2","first-page":"27","article-title":"FSM-Based WiMAX Multimode Interleaver","volume":"6","author":"Upadhyaya B. K.","year":"2012","journal-title":"International Journal of Communication"},{"key":"e_1_2_11_11_2","article-title":"ASIC Implementation of Low-Power Multistandard Interleaver","volume":"121","author":"Sharma R.","year":"2022","journal-title":"Microelectronics Journal"},{"key":"e_1_2_11_12_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2018.12.010"},{"key":"e_1_2_11_13_2","doi-asserted-by":"publisher","DOI":"10.1155\/2012\/948957"},{"key":"e_1_2_11_14_2","first-page":"735","volume-title":"Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering","author":"Sghaier S.","year":"2007"},{"key":"e_1_2_11_15_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2010.07.001"},{"key":"e_1_2_11_16_2","first-page":"1","article-title":"Interleaver Design for MIMO-OFDM on FPGA","author":"Iqbal Z.","year":"2012","journal-title":"IEEE International Symposium on Consumer Electronics"},{"key":"e_1_2_11_17_2","article-title":"IP Core for WLAN Interleaving Using LUT-Based Address Generation","volume":"76","author":"Sghaier M. A.","year":"2020","journal-title":"Microprocessors and Microsystems"},{"key":"e_1_2_11_18_2","first-page":"1","article-title":"FSM-Based Reconfigurable Interleaver for WLAN","author":"Upadhyaya B. K.","year":"2011","journal-title":"Proceedings of an International Conference Focused on Devices and Communication"},{"key":"e_1_2_11_19_2","first-page":"492","article-title":"Efficient FPGA Implementation of an Address Generator for WiMAX Deinterleaver","volume":"60","author":"Upadhyaya B. K.","year":"2013","journal-title":"IEEE Transactions on Circuits and Systems"},{"key":"e_1_2_11_20_2","unstructured":"Xilinx 7 Series FPGAs Configurable Logic Block User Guide 2017."},{"key":"e_1_2_11_21_2","doi-asserted-by":"crossref","unstructured":"PerumalV. K.andJayabalanR. High Speed and Area Efficient Address Generator Architecture for WiMAX Deinterleaver 2022 https:\/\/doi.org\/10.21203\/rs.3.rs-1920241\/v1.","DOI":"10.21203\/rs.3.rs-1920241\/v1"},{"key":"e_1_2_11_22_2","unstructured":"Xilinx UltraScale Architecture and Product Data Sheet: Overview 2018."}],"container-title":["Journal of Electrical and Computer Engineering"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/jece\/2638291","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/full-xml\/10.1155\/jece\/2638291","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/jece\/2638291","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,17]],"date-time":"2026-03-17T20:38:01Z","timestamp":1773779881000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/jece\/2638291"}},"subtitle":[],"editor":[{"given":"Palanisamy","family":"R.","sequence":"additional","affiliation":[],"role":[{"role":"editor","vocabulary":"crossref"}]}],"short-title":[],"issued":{"date-parts":[[2025,1]]},"references-count":22,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2025,1]]}},"alternative-id":["10.1155\/jece\/2638291"],"URL":"https:\/\/doi.org\/10.1155\/jece\/2638291","archive":["Portico"],"relation":{},"ISSN":["2090-0147","2090-0155"],"issn-type":[{"value":"2090-0147","type":"print"},{"value":"2090-0155","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,1]]},"assertion":[{"value":"2025-04-23","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-07-15","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-10-24","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}],"article-number":"2638291"}}