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Several complex signal processing tasks are performed by SDR, and field programmable gate arrays (FPGAs) are the best solution to implement such tasks of SDR. Quadrature phase shift keying (QPSK) is widespread in numerous SDR systems for digital transmission. To generate QPSK signals, modulation approaches such as FPGA, VLSI, and CMOS are used. Analog oscillators are also used to generate carriers for digital transmission systems. Digital oscillators have been chosen to replace analog oscillators in FPGA\u2010based QPSK. Among the design techniques of digital oscillators, we can name the direct digital synthesis (DDS) and the CORDIC algorithm. The two techniques present some drawbacks at the level of memory storage, processing time, and latency. In this paper, we develop an FPGA\u2010based QPSK modulator with a digital oscillator using a numerical solver that utilizes a negative impedance converter (NIC) circuit. The proposed modulator is built and is able to generate the sine and cosine functions. Our proposed modulator is made of an NIC\u2010based digital solver, two multiplexers, three logical arithmetic operators, a flip\u2010flop, and a digital\u2010to\u2010analog converter. The implementation is performed on the IV\u2010EEP4CE115F29C7N chip of the DE2\u2010115 board described in the VHDL language with 64\u2010bit fixed\u2010point words according to IEEE 754 standards. After analysis, the NIC\u2010based modulator presents a signal\u2010to\u2010noise ratio (SNR) of 7.28, an error vector magnitude (EVM) of 49.65%, a bit error rate (BER) of 0.73 for a 4\u2010QAM and an SNR of 12.48, an EVM of 72.81%, and a BER of 0.46 for a 16\u2010QAM. At the experimental level, we have 1002 logic components, 119 registers, 0 memory bits, 0 integrated multipliers, and 153.57\u2009mW of estimated power consumption. The proposed modulator consumes more resources than a direct digital frequency synthesis (DDFS)\u2010based modulator. However, despite the high power consumption, it features no embedded multipliers and no bit of memory used. The digital modulator we propose can be used in cases where low power consumption is required and the storage capacity is not desired, as demonstrated by experimental results.<\/jats:p>","DOI":"10.1155\/jece\/4367062","type":"journal-article","created":{"date-parts":[[2025,12,15]],"date-time":"2025-12-15T14:39:43Z","timestamp":1765809583000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["FPGA\u2010Based Quadrature Phase Shift Keying Modulator With Carrier Derived From Negative Impedance Converter Equation"],"prefix":"10.1155","volume":"2025","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1642-4628","authenticated-orcid":false,"given":"Achille Ecladore Tchahou","family":"Tchendjeu","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4631-529X","authenticated-orcid":false,"given":"Robert","family":"Tchitnga","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2025,12,15]]},"reference":[{"key":"e_1_2_12_1_2","doi-asserted-by":"crossref","unstructured":"SiddiquaM. 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