{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T00:32:13Z","timestamp":1773793933270,"version":"3.50.1"},"reference-count":37,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2025,5,23]],"date-time":"2025-05-23T00:00:00Z","timestamp":1747958400000},"content-version":"vor","delay-in-days":142,"URL":"http:\/\/creativecommons.org\/licenses\/by\/4.0\/"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/doi.wiley.com\/10.1002\/tdm_license_1.1"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["Journal of Electrical and Computer Engineering"],"published-print":{"date-parts":[[2025,1]]},"abstract":"<jats:p>\n                    Time\u2010domain all\u2010digital\u2010phase\u2010locked\u2010loop phase\u2010shift\u2010keying (PSK) demodulators are proposed for BPSK, QPSK, and 8PSK signals. The demodulator architectures are highly suitable for low\u2010voltage nanoscale CMOS techology. Data\u2010bit extraction as well as phase control for loop locking can be effectively achieved in a time domain with simple logic operators such as positive\u2010edge\u2010trigger RESET\/SET (pRSFF) and delay flip flops (DFF). Pulse width of the phase\u2010control signal is sampled and passed on to the digitally\u2010controlled oscillator (DCO) for frequency and phase adjustment. Two different phase control methods have been employed to appropriately alter a duty cycle of the phase\u2010control signal. The first option is performed by multiplexing a single\u2010phase DCO signal as selected by the extracted data bits. The second technique uses\n                    <jats:italic>m<\/jats:italic>\n                    DCO phases simultaneously for phase\u2010control detection with the incoming\n                    <jats:italic>m<\/jats:italic>\n                    \u2010PSK signal. This helps reduce the intertwined loop of the first method to a single\u2010loop structure. This modular BPSK, QPSK, and 8PSK demodulation concept has been successfully verified by measurement with discrete components at a carrier frequency of 100\u2009kHz operating under a 5\u2010V supply.\n                  <\/jats:p>","DOI":"10.1155\/jece\/5560884","type":"journal-article","created":{"date-parts":[[2025,5,24]],"date-time":"2025-05-24T01:49:10Z","timestamp":1748051350000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Time\u2010Domain ADPLL BPSK, QPSK, and 8PSK Demodulators"],"prefix":"10.1155","volume":"2025","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8134-1680","authenticated-orcid":false,"given":"Phanumas","family":"Khumsat","sequence":"first","affiliation":[]},{"given":"Thanabodee","family":"Koyphol","sequence":"additional","affiliation":[]},{"given":"Tan","family":"Thongruk","sequence":"additional","affiliation":[]},{"given":"Tidarat","family":"Inyod","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2025,5,23]]},"reference":[{"key":"e_1_2_10_1_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2713522"},{"key":"e_1_2_10_2_2","volume-title":"Digital and Analog Communication Systems","author":"Leon W.","year":"2007"},{"key":"e_1_2_10_3_2","volume-title":"Modern Wireless Communications","author":"Haykin S.","year":"2005"},{"key":"e_1_2_10_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.918174"},{"key":"e_1_2_10_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2166469"},{"key":"e_1_2_10_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/JLT.2013.2265075"},{"key":"e_1_2_10_7_2","doi-asserted-by":"crossref","unstructured":"LeeS. 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