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A hierarchical sub-modeling methodology was used, starting with a homogenized global model to identify high-stress regions, followed by two levels of sub-models to resolve stresses in a single TFT cell under simulated thermal cool-down from fabrication temperatures. Results identified the highest stress concentrations at the corners of dies near the panel edge. At the device level, the analysis revealed that the critical gate insulator is subjected to a tensile stress of approximately 44.5\u2005MPa and a strain of about 0.1%, a level sufficient to potentially alter electrical performance. Furthermore, other brittle dielectric layers, such as the passivation layer, were predicted to experience significantly higher stresses (approximately 407\u2005MPa), indicating a primary risk of mechanical fracture. The study affirms the mechanical feasibility of the TFT-FOPLP concept but underscores the need for careful stress mitigation in vulnerable regions. The presented modeling framework provides a powerful tool for design-for-reliability by enabling the early prediction of high-stress zones, thereby reducing reliance on physical prototyping. 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