{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T06:01:20Z","timestamp":1740808880590,"version":"3.38.0"},"reference-count":17,"publisher":"SAGE Publications","issue":"4","license":[{"start":{"date-parts":[[2002,4,1]],"date-time":"2002-04-01T00:00:00Z","timestamp":1017619200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/journals.sagepub.com\/page\/policies\/text-and-data-mining-license"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["SIMULATION"],"published-print":{"date-parts":[[2002,4]]},"abstract":"<jats:p> The performance of an integrated architecture for full-duplex IP-over-ATM processing is evaluated through detailed simulation. The architecture combines processing, memory, and multiple direct-memory-access engines for single-chip implementation. The simulation models the segmentation and reassembly operations needed to translate IP frames to and from a fixed ATM cell size. A key operation is the insertion of a virtual path and virtual channel identifier (VPI\/VCI) into the outgoing ATM cells. Software-based VPI\/VCI insertion provides flexibility but requires the on-chip processor to perform this function. Hardware-based VPI\/VCI insertion is an optimization that requires one of the direct-memory-access engines to perform this task. The two approaches are evaluated through simulated execution of representative control software with detailed modeling of all on-chip components. Results indicate that software-based VPI\/VCI insertion supports full-duplex traffic at 475 Mbps on a 500-MHz processor and that hardware-based VPI\/VCI insertion supports full-duplex traffic at 560 Mbps on a 500-MHz processor. <\/jats:p>","DOI":"10.1177\/0037549702078004543","type":"journal-article","created":{"date-parts":[[2003,7,19]],"date-time":"2003-07-19T02:50:52Z","timestamp":1058583052000},"page":"249-257","source":"Crossref","is-referenced-by-count":1,"title":["Simulation of an Integrated Architecture for IP-over-ATM Frame Processing"],"prefix":"10.1177","volume":"78","author":[{"given":"Peter M.","family":"Ewert","sequence":"first","affiliation":[{"name":"Access and Switching Group, Intel Corporation, Hillsboro, Oregon, USA 97124,"}]},{"given":"Naraig","family":"Manjikian","sequence":"additional","affiliation":[{"name":"Dept. of Elec.\/Comp. Eng., Queen\u2019s University, Kingston, Ontario, Canada K7L 3N6,"}]}],"member":"179","published-online":{"date-parts":[[2002,4,1]]},"reference":[{"volume-title":"ATM theory and application","year":"1994","author":"McDysan, D. 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