{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,4]],"date-time":"2026-05-04T13:43:49Z","timestamp":1777902229492,"version":"3.51.4"},"reference-count":15,"publisher":"SAGE Publications","issue":"7","license":[{"start":{"date-parts":[[2012,1,19]],"date-time":"2012-01-19T00:00:00Z","timestamp":1326931200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/journals.sagepub.com\/page\/policies\/text-and-data-mining-license"}],"content-domain":{"domain":["journals.sagepub.com"],"crossmark-restriction":true},"short-container-title":["SIMULATION"],"published-print":{"date-parts":[[2012,7]]},"abstract":"<jats:p>In this paper we present the design and implementation of a parallel network simulator to manipulate the shared-memory packet buffer in a network interface card (NIC) for a network terminal. The proposed simulator consists of two components, input generator and buffer management simulator. The simulator flexibly accommodates either a dynamic or a static packet buffer management algorithm for a high-speed Ethernet to deliver fast and accurate clock-cycle level data analysis. In addition, it is transparent to trace and analyze the concurrent operations in the packet buffer and, thus, the simulator contributes to developing efficient buffer management algorithms.<\/jats:p>","DOI":"10.1177\/0037549711433494","type":"journal-article","created":{"date-parts":[[2012,1,20]],"date-time":"2012-01-20T02:45:04Z","timestamp":1327027504000},"page":"884-891","update-policy":"https:\/\/doi.org\/10.1177\/sage-journals-update-policy","source":"Crossref","is-referenced-by-count":0,"title":["A parallel simulator for network terminal packet buffer"],"prefix":"10.1177","volume":"88","author":[{"given":"Yul","family":"Chu","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, University of Texas Pan American, Edinburg, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jin Hwan","family":"Park","sequence":"additional","affiliation":[{"name":"Department of Computer Science, California State University, Fresno, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yan","family":"Bai","sequence":"additional","affiliation":[{"name":"Institute of Technology, University of Washington, Tacoma, WA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jae Sok","family":"Son","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, University of Texas Pan American, Edinburg, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanjeev","family":"Kumar","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, University of Texas Pan American, Edinburg, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"179","published-online":{"date-parts":[[2012,1,19]]},"reference":[{"key":"bibr1-0037549711433494","doi-asserted-by":"publisher","DOI":"10.1109\/49.917702"},{"key":"bibr2-0037549711433494","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.2001.934483"},{"key":"bibr3-0037549711433494","volume-title":"Computer Networks","author":"Tanenbaum A","year":"2002","edition":"4"},{"key":"bibr4-0037549711433494","first-page":"414","volume-title":"IEEE Proceedings on Computer Design: VLSI in Computers and Processors","volume":"2","author":"Henriksson T"},{"key":"bibr5-0037549711433494","first-page":"1026","volume-title":"Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems","volume":"3","author":"Nordqvist U"},{"key":"bibr6-0037549711433494","volume-title":"Proceedings of the 10th IEEE Symposium on Computers and Communications (ISCC\u201905)","author":"Rajan V"},{"key":"bibr7-0037549711433494","doi-asserted-by":"publisher","DOI":"10.1109\/COMST.2000.5340716"},{"key":"bibr8-0037549711433494","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:20020443"},{"key":"bibr9-0037549711433494","unstructured":"Henriksson T. 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