{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,4]],"date-time":"2026-05-04T13:47:18Z","timestamp":1777902438454,"version":"3.51.4"},"reference-count":35,"publisher":"SAGE Publications","issue":"8","license":[{"start":{"date-parts":[[2018,9,10]],"date-time":"2018-09-10T00:00:00Z","timestamp":1536537600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/journals.sagepub.com\/page\/policies\/text-and-data-mining-license"}],"content-domain":{"domain":["journals.sagepub.com"],"crossmark-restriction":true},"short-container-title":["SIMULATION"],"published-print":{"date-parts":[[2019,8]]},"abstract":"<jats:p>Field Programmable Gate Arrays (FPGAs), due to their programmability, have become a popular design choice for control and processing blocks of modern-day digital design. However, this flexibility makes them larger, slower, and less power-efficient when compared to Application Specific Integrated Circuits (ASICs). On the other hand, ASICs have their own drawbacks, such as lack of programmability and inflexibility. One potential solution is specialized fine-grained reconfigurable architectures that have improved flexibility over ASICs and better resource utilization than FPGAs. However, designing a fine-grained reconfigurable architecture is a daunting task in itself due to lack of high-level design-flow support. This article proposes an automated design-flow for the system-level simulation, optimization, and resource estimation of generic as well as custom fine-grained reconfigurable architectures. The proposed framework is generic in nature as it can be used for both control-oriented and compute-intensive applications and then generates a homogeneous or heterogeneous reconfigurable architecture for them. Four sets of homogeneous and heterogeneous benchmarks are used in this work to show the efficacy of our proposed design-flow, and simulation results reveal that our framework can generate both generic and custom fine-grained reconfigurable architectures. Moreover, the area and power estimations show that auto-generated domain-specific reconfigurable architectures are 76% and 73% more area and power-efficient, respectively, than generic FPGA-based implementations. These results are consistent with the savings reported for manual designs in the literature.<\/jats:p>","DOI":"10.1177\/0037549718796272","type":"journal-article","created":{"date-parts":[[2018,9,10]],"date-time":"2018-09-10T05:57:53Z","timestamp":1536559073000},"page":"737-751","update-policy":"https:\/\/doi.org\/10.1177\/sage-journals-update-policy","source":"Crossref","is-referenced-by-count":0,"title":["A framework for high-level simulation and optimization of fine-grained reconfigurable architectures"],"prefix":"10.1177","volume":"95","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9892-5201","authenticated-orcid":false,"given":"Muhammad Adeel","family":"Pasha","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, SBASSE, LUMS, Pakistan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Umer","family":"Farooq","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering Department, Dhofar University, Oman"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bilal","family":"Siddiqui","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Purdue University, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"179","published-online":{"date-parts":[[2018,9,10]]},"reference":[{"key":"bibr1-0037549718796272","first-page":"41","volume-title":"proceedings of the IEEE international conference on field programmable technology (FPT)","author":"Lemieux G"},{"key":"bibr2-0037549718796272","doi-asserted-by":"publisher","DOI":"10.1145\/1059876.1059881"},{"key":"bibr3-0037549718796272","first-page":"33","volume-title":"proceedings of the ACM\/SIGDA international symposium on FPGA","author":"Luu J"},{"key":"bibr4-0037549718796272","unstructured":"University of California Berkeley. Berkeley Logic Interchange Format (BLIF). Tech Report, UCB, 28July1992."},{"key":"bibr5-0037549718796272","first-page":"149","volume-title":"18th IEEE annual international symposium on field-programmable custom computing machines (FCCM)","author":"Jamieson P"},{"key":"bibr6-0037549718796272","unstructured":"Berkeley. ABC: a system for sequential synthesis and verification, http:\/\/people.eecs.berkeley.edu\/~alanmi\/abc\/ (accessed 30 July 2018)."},{"key":"bibr7-0037549718796272","first-page":"77","volume-title":"proceedings of the ACM\/SIGDA international symposium on field programmable gate arrays (FPGA)","author":"Rose J"},{"key":"bibr8-0037549718796272","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2015.7127382"},{"key":"bibr9-0037549718796272","first-page":"112","volume-title":"proceedings of the IEEE international conference on field programmable technology (FPT) 2009","author":"Parvez H"},{"key":"bibr10-0037549718796272","unstructured":"Yang S. Logic Synthesis and Optimization Benchmarks, Version 3.0. Microelectronics Center of North Carolina (MCNC), Raleigh, https:\/\/ddd.fit.cvut.cz\/prj\/Benchmarks\/LGSynth91.pdf (1991, accessed 30 July 2018)."},{"key":"bibr11-0037549718796272","unstructured":"VPR. Sample VPR 5.0.2. Benchmarks for heterogeneous FPGAs, https:\/\/github.com\/verilog-to-routing\/vtr-verilog-to-routing (2016, accessed 30 July 2018)."},{"key":"bibr12-0037549718796272","unstructured":"Open Cores. The Reference Community for Free and Open Source Gateware IP Cores, http:\/\/www.opencores.org\/ (accessed 30 July 2018)."},{"key":"bibr13-0037549718796272","doi-asserted-by":"publisher","DOI":"10.1145\/2514740"},{"key":"bibr14-0037549718796272","unstructured":"Xilinx. Vivado Design Suite - HLx Editions, http:\/\/www.xilinx.com\/products\/design-tools\/vivado.html (accessed 30 July 2018)."},{"key":"bibr15-0037549718796272","first-page":"150","volume-title":"27th international conference on advanced information networking and applications workshops (WAINA)","author":"Hiraiwa J"},{"key":"bibr16-0037549718796272","first-page":"362","volume-title":"international conference on field programmable technology (FPT)","author":"Winterstein F"},{"key":"bibr17-0037549718796272","first-page":"97","volume-title":"IEEE 23rd annual international symposium on field-programmable custom computing machines (FCCM)","author":"Andrade J"},{"key":"bibr18-0037549718796272","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2017.2727221"},{"key":"bibr19-0037549718796272","unstructured":"Intel. Intel Quartus Prime Software, https:\/\/www.altera.com\/products\/design-software\/fpga-design\/quartus-prime\/download.html (accessed 30 July 2018)."},{"key":"bibr20-0037549718796272","first-page":"127","volume-title":"IEEE 18th annual international symposium on field-programmable custom computing machines (FCCM)","author":"Villarreal J"},{"key":"bibr21-0037549718796272","first-page":"12","volume-title":"proceedings of the 14th ACM\/IEEE international symposium on field programmable gate arrays (FPGA)","author":"Beauchamp M"},{"key":"bibr22-0037549718796272","first-page":"35","volume-title":"IEEE 14th annual international symposium on field-programmable custom computing machines (FCCM)","author":"Ho C"},{"key":"bibr23-0037549718796272","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2017.06.001"},{"key":"bibr24-0037549718796272","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"bibr25-0037549718796272","first-page":"103","volume-title":"proceedings of the 2004 international symposium on physical design (ISPD)","author":"Wu K"},{"key":"bibr26-0037549718796272","first-page":"1","volume-title":"9th international symposium on reconfigurable and communication-centric systems-on-chip (ReCoSoC)","author":"Qureshi MA"},{"key":"bibr27-0037549718796272","first-page":"127","volume-title":"proceedings of the IEEE 16th international conference on application-specific systems, architectures and processors (ASAP)","author":"L\u2019Hours L"},{"key":"bibr28-0037549718796272","unstructured":"The Eclipse Foundation. Eclipse Modeling Framework (EMF), http:\/\/www.eclipse.org\/modeling\/emf\/ (accessed 30 July 2018)."},{"key":"bibr29-0037549718796272","unstructured":"Sentovich E, Singh K, Lavagno L, et al. SIS: a system for sequential circuit synthesis. University of California, Berkeley, Tech. Rep. UCB\/ERLM92\/ 41, 1992."},{"key":"bibr30-0037549718796272","first-page":"37","volume-title":"proceedings of the 7th ACM\/SIGDA international symposium on field programmable gate arrays (FPGA)","author":"Marquart A"},{"key":"bibr31-0037549718796272","first-page":"225","volume-title":"proceedings of the 2004 IEEE international conference on field-programmable technology (FPT)","author":"Malhotra S"},{"key":"bibr32-0037549718796272","doi-asserted-by":"publisher","DOI":"10.1126\/science.220.4598.671"},{"key":"bibr33-0037549718796272","first-page":"111","volume-title":"proceedings of the 3rd international ACM symposium on field-programmable gate arrays (FPGA)","author":"McMurchie L"},{"key":"bibr34-0037549718796272","unstructured":"Engelhardt M. LTSpice\/SwitcherCAD IV, http:\/\/www.analog.com\/en\/design-center\/design-tools-and-calculators.html (accessed 30 July 2018)."},{"key":"bibr35-0037549718796272","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"}],"container-title":["SIMULATION"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.1177\/0037549718796272","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/journals.sagepub.com\/doi\/full-xml\/10.1177\/0037549718796272","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.1177\/0037549718796272","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T11:29:37Z","timestamp":1777634977000},"score":1,"resource":{"primary":{"URL":"https:\/\/journals.sagepub.com\/doi\/10.1177\/0037549718796272"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9,10]]},"references-count":35,"journal-issue":{"issue":"8","published-print":{"date-parts":[[2019,8]]}},"alternative-id":["10.1177\/0037549718796272"],"URL":"https:\/\/doi.org\/10.1177\/0037549718796272","relation":{},"ISSN":["0037-5497","1741-3133"],"issn-type":[{"value":"0037-5497","type":"print"},{"value":"1741-3133","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,9,10]]}}}