{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,4]],"date-time":"2026-05-04T13:35:45Z","timestamp":1777901745616,"version":"3.51.4"},"reference-count":23,"publisher":"SAGE Publications","issue":"2","license":[{"start":{"date-parts":[[1993,2,1]],"date-time":"1993-02-01T00:00:00Z","timestamp":728524800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/journals.sagepub.com\/page\/policies\/text-and-data-mining-license"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["SIMULATION"],"published-print":{"date-parts":[[1993,2]]},"abstract":"<jats:p>Advances in VLSI technologies have led to the implementation of very large and complex systems on a single chip. Current Computer Aided Design (CAD) tools are being pushed to their limits in order to keep up with increasing chip complexity. One of the main problems facing current CAD tools is the large amount of memory required when dealing with large systems. Most tools represent the circuit as a collection of primitives and shared information is duplicated. This paper discusses an approach for hierarchical switch-level simulation of digital circuits. The approach exploits the hierarchy to reduce the memory require ments of the simulation, allowing the simulation of circuits that are too large to simulate at the flat level. In addition, parts of the circuit can be replaced with automati cally generated software models, thus increasing the simulation speed without sacrificing accuracy. The approach has been implemented in a hierarchical switch-level simulator, CHAMP. The program allows for user-supplied behavioral models, assignable delays, and bidirectional signal flow inside circuit blocks that are repre sented as transistor networks as well as across the boundaries of higher level blocks.<\/jats:p>","DOI":"10.1177\/003754979306000202","type":"journal-article","created":{"date-parts":[[2008,3,29]],"date-time":"2008-03-29T13:23:43Z","timestamp":1206797023000},"page":"79-91","source":"Crossref","is-referenced-by-count":0,"title":["Concurrent Hierarchical and Multilevel Simulation of VLSI Circuits"],"prefix":"10.1177","volume":"60","author":[{"given":"Robert B.","family":"Mueller-Thuns","sequence":"first","affiliation":[{"name":"Cadence Design System Inc. 555 River Oaks Pkwy, M15381 San Jose, CA 95134"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joseph T.","family":"Rahmeh","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering University of Texas at Austin Austin, TX 78712"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jacob A.","family":"Abraham","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering University of Texas at Austin Austin, TX 78712"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jalal A.","family":"Wehbeh","sequence":"additional","affiliation":[{"name":"Center for Reliable & High-Performance Computing Coordinated Science Lab University of Illinois at Urbana-Champaign Urbana, IL 61801"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daniel G.","family":"Saab","sequence":"additional","affiliation":[{"name":"Center for Reliable & High-Performance Computing Coordinated Science Lab University of Illinois at Urbana-Champaign Urbana, IL 61801"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"179","published-online":{"date-parts":[[1993,2,1]]},"reference":[{"key":"atypb1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-95424-5"},{"key":"atypb2","volume-title":"Proceedings of the IEEE International Conference on Circuits and Computers","author":"Banerjee"},{"key":"atypb3","volume-title":"Proceedings of the IEEE International Conference on Computer-Aided Design","author":"I.N. Hajj"},{"key":"atypb4","volume-title":"Custom Integrated Circuit Conference","author":"Y.M. El-Ziq"},{"issue":"6","key":"atypb5","first-page":"24","author":"R.E. Bryant","year":"1983","journal-title":"VLSI Design"},{"key":"atypb6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.1676408"},{"key":"atypb7","volume-title":"Proceedings of the 19th ACM Design Automation Workshop","author":"M.R. Lightner"},{"key":"atypb8","volume-title":"Proc. of the 19th Design Automation Conference","author":"A.K. Bose"},{"key":"atypb9","volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems","author":"G. Ditlow"},{"key":"atypb10","volume-title":"Proceedings of the 24th ACM\/IEEE Design Automation Conference","author":"R.E. Bryant"},{"key":"atypb11","volume-title":"18th ACM\/IEEE Design Automation Conf","author":"R.E. Bryant"},{"key":"atypb12","volume-title":"Proceedings of the IEEE International Conference on Computer Design","author":"C.J. Terman"},{"key":"atypb13","volume-title":"Proc. of the IEEE International Test Conference","author":"W.A. Rogers"},{"key":"atypb14","volume-title":"Proc. IEEE Int. Symp. Circuits and Systems","author":"D.D. Hill"},{"key":"atypb15","volume-title":"MC68000 Programmer's Reference Manual","author":"Motorola Corporation","year":"1986"},{"key":"atypb16","volume-title":"The C Programming Language","author":"B.W. Kernighan","year":"1978"},{"key":"atypb17","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4613-2821-6"},{"key":"atypb18","volume-title":"25th Design Automation Conference","author":"D.L. Beatty"},{"key":"atypb19","volume-title":"Logic and Fault Simulation of VLSI Circuits Including Hierarchical Techniques","author":"D.G. Saab","year":"1988"},{"key":"atypb20","volume-title":"Advances in CAD for VLSI: Circuit Analysis, Simulation, and Design","author":"A.E. Ruehli","year":"1987"},{"key":"atypb21","doi-asserted-by":"publisher","DOI":"10.1109\/43.3214"},{"key":"atypb22","volume-title":"The Design and Analysis of Computer Algorithms","author":"A.H. Aho","year":"1974"},{"key":"atypb23","volume-title":"Proceedings of the 25th ACM\/IEEE Design Automation Conference","author":"D.G. Saab"}],"container-title":["SIMULATION"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.1177\/003754979306000202","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.1177\/003754979306000202","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T11:08:38Z","timestamp":1777633718000},"score":1,"resource":{"primary":{"URL":"https:\/\/journals.sagepub.com\/doi\/10.1177\/003754979306000202"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1993,2]]},"references-count":23,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1993,2]]}},"alternative-id":["10.1177\/003754979306000202"],"URL":"https:\/\/doi.org\/10.1177\/003754979306000202","relation":{},"ISSN":["0037-5497","1741-3133"],"issn-type":[{"value":"0037-5497","type":"print"},{"value":"1741-3133","type":"electronic"}],"subject":[],"published":{"date-parts":[[1993,2]]}}}