{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,4]],"date-time":"2025-03-04T05:43:05Z","timestamp":1741066985057,"version":"3.38.0"},"reference-count":9,"publisher":"SAGE Publications","issue":"4","license":[{"start":{"date-parts":[[1993,4,1]],"date-time":"1993-04-01T00:00:00Z","timestamp":733622400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/journals.sagepub.com\/page\/policies\/text-and-data-mining-license"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["SIMULATION"],"published-print":{"date-parts":[[1993,4]]},"abstract":"<jats:p> For shared bus multiprocessors operated in multiprogramming mode, the addition of second-level caches tends to significantly increase system performance. Trace-driven simulation was employed to obtain performance measurements over a range of system parameters, with the cache sizes at both levels being the parameters of most interest. For both light and heavy system loading, the addition of second-level caches was found to boost system performance. For heavily loaded multiprocessor cases, the workload-averaged percentage increases in performance ranged from 187% with 32k byte first-level caches to 507% with 4k byte first-level caches when 128k byte second- level caches were added. The main memory configuration and number of processors largely dictates the performance of a shared bus multiprocessor running in multiprogramming mode. The addition of larger second-level caches to the system results in increased system performance over a range of system configurations and workloads. <\/jats:p>","DOI":"10.1177\/003754979306000402","type":"journal-article","created":{"date-parts":[[2008,3,29]],"date-time":"2008-03-29T17:23:43Z","timestamp":1206811423000},"page":"222-231","source":"Crossref","is-referenced-by-count":1,"title":["Two-Level Cache Performance for Multiprocessors"],"prefix":"10.1177","volume":"60","author":[{"given":"Stanley L.","family":"Zimmerman","sequence":"first","affiliation":[{"name":"Rockwell International 400 Collins Rd., NE Cedar Rapids, IA 52498"}]},{"given":"J.P.","family":"Robinson","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering University of Iowa Iowa City, Iowa 52242"}]}],"member":"179","published-online":{"date-parts":[[1993,4,1]]},"reference":[{"volume-title":"\"High Performance Cache Coherence Protocols For Shared-Bus Multiprocessors.\" Technical Report TR-86-06-02","year":"1986","author":"Archibald, J.","key":"atypb1"},{"doi-asserted-by":"publisher","key":"atypb2","DOI":"10.1145\/633625.52409"},{"doi-asserted-by":"publisher","key":"atypb3","DOI":"10.1016\/0743-7315(89)90001-4"},{"volume-title":"\"Multimax Technical Summary.\"","year":"1986","author":"Encore Computer Corporation.","key":"atypb4"},{"key":"atypb5","first-page":"114","author":"Przybylski, S.","year":"1989","journal-title":"Proceedings of the 16th Annual International Symposium on Computer Architecture"},{"volume-title":"\"Sequent Guide to Parallel Programming.\"","year":"1987","author":"Sequent Computer Systems, Inc.","key":"atypb6"},{"doi-asserted-by":"publisher","key":"atypb7","DOI":"10.1145\/633625.52410"},{"doi-asserted-by":"publisher","key":"atypb8","DOI":"10.1145\/356887.356892"},{"volume-title":"\"The SPARC Architecture Manual.\"","year":"1989","author":"Sun Microsystems, Inc.","key":"atypb9"}],"container-title":["SIMULATION"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.1177\/003754979306000402","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.1177\/003754979306000402","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,3]],"date-time":"2025-03-03T14:33:49Z","timestamp":1741012429000},"score":1,"resource":{"primary":{"URL":"https:\/\/journals.sagepub.com\/doi\/10.1177\/003754979306000402"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1993,4]]},"references-count":9,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1993,4]]}},"alternative-id":["10.1177\/003754979306000402"],"URL":"https:\/\/doi.org\/10.1177\/003754979306000402","relation":{},"ISSN":["0037-5497","1741-3133"],"issn-type":[{"type":"print","value":"0037-5497"},{"type":"electronic","value":"1741-3133"}],"subject":[],"published":{"date-parts":[[1993,4]]}}}