{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,4]],"date-time":"2026-05-04T13:36:06Z","timestamp":1777901766994,"version":"3.51.4"},"reference-count":16,"publisher":"SAGE Publications","issue":"1","license":[{"start":{"date-parts":[[1995,7,1]],"date-time":"1995-07-01T00:00:00Z","timestamp":804556800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/journals.sagepub.com\/page\/policies\/text-and-data-mining-license"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["SIMULATION"],"published-print":{"date-parts":[[1995,7]]},"abstract":"<jats:p>A particularly challenging neural network application requiring high-speed and intensive image processing capability is target acquisition and discrimination. It requires spatio-temporal recognition of point and resolved targets at high speeds. A reconfigur able neural architecture may discriminate targets from clutter or classify targets once resolved. By mating a 64 x 64 pixel array infrared (IR) image sensor to a 3-D stack (cube) of 64 neural-net ICs along respective edges, every pixel would directly input to a neural network, thereby processing the infor-mation with full parallelism. Being mated to the infrared sensor array, the cube would operate at 90\u00b0K temperature with &lt;250 nanosecond signal processing speed and a low power consumption of only -2 watts. For low power and compactness in hardware, the emphasis has been on parallelism and analog signal processing. A versatile reconfigurable circuit is presented that offers a variety of neural architectures: multilayer perceptron, template matching with winner-take-all (WTA) circuitry, and a new architecture of cascade backpropagation (CBP). Special designs of analog neuron and synapse implemented in VLSI are presented which bear out high speed response both at room and low temperatures with synapse-neuron signal propagation times of \u223c100 ns. The CBP learning algorithm is illustrated by solving in simulation the nonlinear 6-bit parity problem. Results show that this algorithm is robust even with synaptic resolutions limited to 5 bits. Therefore, it is particularly suitable for hardware implementation.<\/jats:p>","DOI":"10.1177\/003754979506500103","type":"journal-article","created":{"date-parts":[[2007,3,18]],"date-time":"2007-03-18T03:46:49Z","timestamp":1174189609000},"page":"11-25","source":"Crossref","is-referenced-by-count":1,"title":["Analog 3-D Neuroprocessor for Fast Frame Focal Plane Image Processing"],"prefix":"10.1177","volume":"65","author":[{"given":"Tuan","family":"Duong","sequence":"first","affiliation":[{"name":"Center for Space Microelectronics Technology Jet Propulsion Laboratory California Institute of Technology 4800 Oak Grove Dr. Pasadena, CA 91109"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sabrina","family":"Kemeny","sequence":"additional","affiliation":[{"name":"Center for Space Microelectronics Technology Jet Propulsion Laboratory California Institute of Technology 4800 Oak Grove Dr. Pasadena, CA 91109"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Taher","family":"Daud","sequence":"additional","affiliation":[{"name":"Center for Space Microelectronics Technology Jet Propulsion Laboratory California Institute of Technology 4800 Oak Grove Dr. Pasadena, CA 91109"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anil","family":"Thakoor","sequence":"additional","affiliation":[{"name":"Center for Space Microelectronics Technology Jet Propulsion Laboratory California Institute of Technology 4800 Oak Grove Dr. Pasadena, CA 91109"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chris","family":"Saunders","sequence":"additional","affiliation":[{"name":"Irvine Sensors Corporation 3001 Redhill Avenue - Costa Mesa, CA 92626"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"John","family":"Carson","sequence":"additional","affiliation":[{"name":"Irvine Sensors Corporation 3001 Redhill Avenue - Costa Mesa, CA 92626"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"179","published-online":{"date-parts":[[1995,7,1]]},"reference":[{"key":"atypb1","volume-title":"Proceedings of the IEEE International Conference on Neural Networks"},{"key":"atypb2","doi-asserted-by":"publisher","DOI":"10.1016\/0893-6080(91)90039-8"},{"key":"atypb3","doi-asserted-by":"publisher","DOI":"10.1109\/41.170975"},{"key":"atypb4","volume-title":"Proceedings of the IEEE , International Conference on Neural Networks","author":"T. Duong"},{"key":"atypb5","doi-asserted-by":"publisher","DOI":"10.1088\/0954-898X_1_1_003"},{"key":"atypb6","volume-title":"Proc. SPIE, vol. 1541, Infrared Sensors:Detectors, Electronics, and Signal Processing","author":"John Carson"},{"key":"atypb7","volume-title":"Private communication","author":"T. Duong"},{"key":"atypb8","unstructured":"S.E. Fahlman and C. Lebiere, \"The cascade correlation learning architecture,\" in: Advances in Neural Information Processing Systems II, Ed: D. Touretzky, pp 524-532, Morgan Kaufmann , San Mateo, 1990."},{"key":"atypb9","volume-title":"Learning in neural networks: VLSI implementaticm strategies","author":"T.A. Duong","year":"1995"},{"key":"atypb10","doi-asserted-by":"publisher","DOI":"10.1117\/12.205248"},{"key":"atypb11","volume-title":"Proceedings of the 2nd IEE International Conference on Artificial Neural Networks","author":"A.M. Chen"},{"key":"atypb12","doi-asserted-by":"publisher","DOI":"10.1162\/neco.1990.2.3.363"},{"key":"atypb13","doi-asserted-by":"crossref","volume-title":"Cascade error projection learning algorithm","author":"T. Duong","DOI":"10.1109\/ICNN.1996.548896"},{"key":"atypb14","volume-title":"Linear Algebra and its Applications","author":"G. Strang","year":"1988","edition":"3"},{"key":"atypb15","volume-title":"Proceedings of the IEEE Ist. International Conference on Neural Networks","author":"D.B. Parker"},{"key":"atypb16","doi-asserted-by":"publisher","DOI":"10.1109\/72.143374"}],"container-title":["SIMULATION"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.1177\/003754979506500103","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.1177\/003754979506500103","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T11:10:20Z","timestamp":1777633820000},"score":1,"resource":{"primary":{"URL":"https:\/\/journals.sagepub.com\/doi\/10.1177\/003754979506500103"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,7]]},"references-count":16,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1995,7]]}},"alternative-id":["10.1177\/003754979506500103"],"URL":"https:\/\/doi.org\/10.1177\/003754979506500103","relation":{},"ISSN":["0037-5497","1741-3133"],"issn-type":[{"value":"0037-5497","type":"print"},{"value":"1741-3133","type":"electronic"}],"subject":[],"published":{"date-parts":[[1995,7]]}}}