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To address this challenging problem, a control-theoretic approach is presented in this paper for adaptive cache-fair multiprocessor scheduling. The adaptive cache-fair multiprocessor scheduling uses process models to estimate the shared cache size requirements and the instruction count variations of the threads running on multiprocessor cores. Then, it feeds the estimated information back to an adaptive controller. Designed from the process models, the controller decides processor cycle re-allocation through model computation to maintain the instruction counts of the multiple threads at their desired values. The effectiveness of the adaptive cache-fair multiprocessor scheduling is demonstrated through examples. <\/jats:p>","DOI":"10.1177\/0142331217715064","type":"journal-article","created":{"date-parts":[[2017,11,13]],"date-time":"2017-11-13T14:04:30Z","timestamp":1510581870000},"page":"3095-3104","update-policy":"https:\/\/doi.org\/10.1177\/sage-journals-update-policy","source":"Crossref","is-referenced-by-count":0,"title":["Control-theoretic adaptive cache-fair scheduling of chip multiprocessor systems"],"prefix":"10.1177","volume":"40","author":[{"given":"Huseyin G","family":"Arslan","sequence":"first","affiliation":[{"name":"School of Electrical Engineering and Computer Science, Queensland University of Technology, Australia"}]},{"given":"Yu-Chu","family":"Tian","sequence":"additional","affiliation":[{"name":"School of Electrical Engineering and Computer Science, Queensland University of Technology, Australia"},{"name":"College of Information Engineering, Taiyuan University of Technology, China"}]},{"given":"Fenglian","family":"Li","sequence":"additional","affiliation":[{"name":"School of Electrical Engineering and Computer Science, Queensland University of Technology, Australia"},{"name":"College of Information Engineering, Taiyuan University of Technology, China"}]},{"given":"Chen","family":"Peng","sequence":"additional","affiliation":[{"name":"Shanghai Key Laboratory of Power Station Automation Technology, Shanghai University, China"}]},{"given":"Min-Rui","family":"Fei","sequence":"additional","affiliation":[{"name":"Shanghai Key Laboratory of Power Station Automation Technology, Shanghai University, China"}]}],"member":"179","published-online":{"date-parts":[[2017,11,13]]},"reference":[{"key":"bibr1-0142331217715064","doi-asserted-by":"publisher","DOI":"10.1109\/EMRTS.2000.853990"},{"key":"bibr2-0142331217715064","unstructured":"Arslan HG (2011) Adaptive cache aware multiprocessor scheduling framework. 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