{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,21]],"date-time":"2026-03-21T21:15:00Z","timestamp":1774127700813,"version":"3.50.1"},"reference-count":9,"publisher":"SAGE Publications","issue":"3","license":[{"start":{"date-parts":[[2000,8,1]],"date-time":"2000-08-01T00:00:00Z","timestamp":965088000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/journals.sagepub.com\/page\/policies\/text-and-data-mining-license"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["The International Journal of High Performance Computing Applications"],"published-print":{"date-parts":[[2000,8]]},"abstract":"<jats:p> The purpose of the PAPI project is to specify a standard application programming interface (API) for accessing hardware performance counters available on most modern microprocessors. These counters exist as a small set of registers that count events, which are occurrences of specific signals and states related to the processor\u2019s function. Monitoring these events facilitates correlation between the structure of source\/object code and the efficiency of the mapping of that code to the underlying architecture. This correlation has a variety of uses in performance analysis, including hand tuning, compiler optimization, debugging, benchmarking, monitoring, and performance modeling. In addition, it is hoped that this information will prove useful in the development of new compilation technology as well as in steering architectural development toward alleviating commonly occurring bottlenecks in high performance computing. <\/jats:p>","DOI":"10.1177\/109434200001400303","type":"journal-article","created":{"date-parts":[[2005,3,8]],"date-time":"2005-03-08T19:23:06Z","timestamp":1110309786000},"page":"189-204","source":"Crossref","is-referenced-by-count":494,"title":["A Portable Programming Interface for Performance Evaluation on Modern Processors"],"prefix":"10.1177","volume":"14","author":[{"given":"S.","family":"Browne","sequence":"first","affiliation":[{"name":"Computer Science Department, University of Tennessee, Knoxville,\r                        Tennessee, U.S.A."}]},{"given":"J.","family":"Dongarra","sequence":"additional","affiliation":[{"name":"Computer Science Department, University of Tennessee, Knoxville, and Oak\r                        Ridge Laboratory, Tennessee, U.S.A."}]},{"given":"N.","family":"Garner","sequence":"additional","affiliation":[{"name":"Computer Science Department, University of Tennessee, Knoxville,\r                        Tennessee, U.S.A."}]},{"given":"G.","family":"Ho","sequence":"additional","affiliation":[{"name":"Computer Science Department, University of Tennessee, Knoxville,\r                        Tennessee, U.S.A."}]},{"given":"P.","family":"Mucci","sequence":"additional","affiliation":[{"name":"Computer Science Department, University of Tennessee, Knoxville,\r                        Tennessee, U.S.A.,"}]}],"member":"179","published-online":{"date-parts":[[2000,8,1]]},"reference":[{"key":"atypb1","volume-title":"POWER3 Introduction and Tuning Guide","author":"Andersson, S.","year":"1998"},{"key":"atypb2","volume-title":"PCL\u2014the Performance Counter Library: A Common Interface to Access Hardware Performance Counters on Microprocessors, Version 1.3","author":"Berrendorf, R."},{"key":"atypb3","volume-title":"Beyond RISC: The post-RISC architecture","author":"Brehob, M.","year":"1996"},{"key":"atypb4","volume-title":"Origin 2000 and Onyx2 Performance Tuning and Optimization Guide","author":"Cortesi, D.","year":"1998"},{"key":"atypb5","first-page":"311","volume-title":"Proceedings of the 1999 International Conference on Parallel Processing","author":"DeRose, L."},{"key":"atypb6","volume-title":"10th International Conference on Computer Performance Evaluation: Modeling Techniques and Tools\u2014Performance Tools\u201998","author":"DeRose, L."},{"key":"atypb7","volume-title":"Computer Architecture: A Quantitative Approach","author":"Hennessy, J. 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