{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,3]],"date-time":"2025-03-03T06:00:07Z","timestamp":1740981607046,"version":"3.38.0"},"reference-count":25,"publisher":"SAGE Publications","issue":"3","license":[{"start":{"date-parts":[[2006,8,1]],"date-time":"2006-08-01T00:00:00Z","timestamp":1154390400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/journals.sagepub.com\/page\/policies\/text-and-data-mining-license"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["The International Journal of High Performance Computing Applications"],"published-print":{"date-parts":[[2006,8]]},"abstract":"<jats:p> In this paper, we propose a hardware performance monitor that provides support not only for measuring cache misses and the addresses associated with them, but also for determining what data is being evicted from the cache when a miss occurs. We describe how to use this hardware support to efficiently determine the cache behavior of application data structures at the source code level. We also present the results of a simulation-based study of this technique, in which we examined the overhead, perturbation of results, and usefulness of collecting this information. <\/jats:p>","DOI":"10.1177\/1094342006067470","type":"journal-article","created":{"date-parts":[[2006,8,7]],"date-time":"2006-08-07T11:32:42Z","timestamp":1154950362000},"page":"353-363","source":"Crossref","is-referenced-by-count":3,"title":["A New Hardware Monitor Design to Measure Data Structure-Specific Cache                 Eviction Information"],"prefix":"10.1177","volume":"20","author":[{"given":"B. R.","family":"Buck","sequence":"first","affiliation":[{"name":"Symantec Corporation, 6750 Alexander Bell Drive, Columbia, MD 21045"}]},{"given":"J. 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