{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,27]],"date-time":"2025-01-27T19:10:12Z","timestamp":1738005012472,"version":"3.33.0"},"reference-count":42,"publisher":"SAGE Publications","issue":"4","license":[{"start":{"date-parts":[[2011,3,8]],"date-time":"2011-03-08T00:00:00Z","timestamp":1299542400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/journals.sagepub.com\/page\/policies\/text-and-data-mining-license"}],"content-domain":{"domain":["journals.sagepub.com"],"crossmark-restriction":true},"short-container-title":["The International Journal of High Performance Computing Applications"],"published-print":{"date-parts":[[2011,11]]},"abstract":"<jats:p> Data prefetching is widely used in high-end computing systems to accelerate data accesses and to bridge the increasing performance gap between processor and memory. Context-based prefetching has become a primary focus of study in recent years due to its general applicability. However, current context-based prefetchers only adopt the context analysis of a single order, which suffers from low prefetching coverage and thus limits the overall prefetching effectiveness. Also, existing approaches usually consider the context of the address stream from a single instruction but not the context of the address stream from all instructions, which further limits the context-based prefetching effectiveness. In this study, we propose a new context-based prefetcher called the Global-aware and Multi-order Context-based (GMC) prefetcher. The GMC prefetcher uses multi-order, local and global context analysis to increase prefetching coverage while maintaining prefetching accuracy. In extensive simulation testing of the SPEC-CPU2006 benchmarks with an enhanced CMP$im simulator, the proposed GMC prefetcher was shown to outperform existing prefetchers and to reduce the data-access latency effectively. The average Instructions Per Cycle (IPC) improvement of SPEC CINT2006 and CFP2006 benchmarks with GMC prefetching was over 55% and 44% respectively. <\/jats:p>","DOI":"10.1177\/1094342010394386","type":"journal-article","created":{"date-parts":[[2011,3,9]],"date-time":"2011-03-09T01:45:32Z","timestamp":1299635132000},"page":"355-370","update-policy":"https:\/\/doi.org\/10.1177\/sage-journals-update-policy","source":"Crossref","is-referenced-by-count":1,"title":["Global-aware and multi-order context-based prefetching for high-performance processors"],"prefix":"10.1177","volume":"25","author":[{"given":"Yong","family":"Chen","sequence":"first","affiliation":[{"name":"Department of Computer Science, Texas Tech University, USA"}]},{"given":"Huaiyu","family":"Zhu","sequence":"additional","affiliation":[{"name":"Department of Computer Science, University of Illinois at Urbana Champaign, USA"}]},{"given":"Philip C.","family":"Roth","sequence":"additional","affiliation":[{"name":"Computer Science and Mathematics Division, Oak Ridge National Laboratory, USA"}]},{"given":"Hui","family":"Jin","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Illinois Institute of Technology, USA"}]},{"given":"Xian-He","family":"Sun","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Illinois Institute of Technology, USA"}]}],"member":"179","published-online":{"date-parts":[[2011,3,8]]},"reference":[{"key":"bibr1-1094342010394386","doi-asserted-by":"publisher","DOI":"10.1145\/945506.945509"},{"key":"bibr2-1094342010394386","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736060"},{"key":"bibr3-1094342010394386","doi-asserted-by":"crossref","unstructured":"Ceze L, Strauss K, Tuck J, Renau J, Torrellas J (2006a) CAVA: Using checkpoint-assisted value prediction to hide L2 misses. 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