{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,12]],"date-time":"2026-03-12T13:58:07Z","timestamp":1773323887544,"version":"3.50.1"},"reference-count":43,"publisher":"SAGE Publications","issue":"2","license":[{"start":{"date-parts":[[2016,7,28]],"date-time":"2016-07-28T00:00:00Z","timestamp":1469664000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/journals.sagepub.com\/page\/policies\/text-and-data-mining-license"}],"content-domain":{"domain":["journals.sagepub.com"],"crossmark-restriction":true},"short-container-title":["The International Journal of High Performance Computing Applications"],"published-print":{"date-parts":[[2017,3]]},"abstract":"<jats:p> The microthreaded many-core architecture is comprised of multiple clusters of fine-grained multi-threaded cores. The management of concurrency is supported in the instruction set architecture of the cores and the computational work in application is asynchronously delegated to different clusters of cores, where the cluster is allocated dynamically. Computer architects are always interested in analyzing the complex interaction amongst the dynamically allocated resources. Generally a detailed simulation with a cycle-accurate simulation of the execution time is used. However, the cycle-accurate simulator for the microthreaded architecture executes at the rate of 100,000 instructions per second, divided over the number of simulated cores. This means that the evaluation of a complex application executing on a contemporary multi-core machine can be very slow. To perform efficient design space exploration we present a co-simulation environment, where the detailed execution of instructions in the pipeline of microthreaded cores and the interactions amongst the hardware components are abstracted. We present the evaluation of the high-level simulation framework against the cycle-accurate simulation framework. The results show that the high-level simulator is faster and less complicated than the cycle-accurate simulator but with the cost of losing accuracy. <\/jats:p>","DOI":"10.1177\/1094342015584495","type":"journal-article","created":{"date-parts":[[2015,5,26]],"date-time":"2015-05-26T01:31:30Z","timestamp":1432603890000},"page":"152-162","update-policy":"https:\/\/doi.org\/10.1177\/sage-journals-update-policy","source":"Crossref","is-referenced-by-count":5,"title":["One-IPC high-level simulation of microthreaded many-core architectures"],"prefix":"10.1177","volume":"31","author":[{"given":"Irfan","family":"Uddin","sequence":"first","affiliation":[{"name":"College of Computer and Information Systems, Al-Yamamah University, Kingdom of Saudi Arabia"}]}],"member":"179","published-online":{"date-parts":[[2016,7,28]]},"reference":[{"key":"bibr1-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1145\/1496909.1496921"},{"key":"bibr2-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"bibr3-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1147\/rd.341.0012"},{"key":"bibr4-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1145\/334012.334028"},{"key":"bibr5-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-21878-1_14"},{"key":"bibr6-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1145\/106972.107003"},{"key":"bibr7-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2008.07.001"},{"key":"bibr8-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063454"},{"key":"bibr9-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1145\/1028176.1006730"},{"key":"bibr10-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1240210"},{"key":"bibr11-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1155\/2007\/82123"},{"key":"bibr12-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.70783"},{"key":"bibr13-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.77"},{"key":"bibr14-1094342015584495","volume-title":"14th workshop on compilers for parallel computing","author":"Grelck C","year":"2009"},{"key":"bibr15-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1145\/1248648.1248654"},{"key":"bibr16-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-70550-5_30"},{"key":"bibr17-1094342015584495","first-page":"37","volume-title":"Advances in Parallel Computing: High Performance Computing and Grids in Action","volume":"16","author":"Jesshope C","year":"2008"},{"key":"bibr18-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1145\/1577129.1577136"},{"key":"bibr19-1094342015584495","first-page":"203","volume-title":"Advances in parallel computing: high performance computing workshop","volume":"14","author":"Jesshope CR","year":"2004"},{"key":"bibr20-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1142\/S0129626406002587"},{"key":"bibr21-1094342015584495","unstructured":"Lankamp M, Poss R, Yang Q, (2013) MGSim - Simulation tools for multi-core processor architectures. Technical Report, University of Amsterdam."},{"key":"bibr22-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419890"},{"key":"bibr23-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.103"},{"key":"bibr24-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1145\/6462.6485"},{"key":"bibr25-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1109\/SIMSYM.2002.1000093"},{"key":"bibr26-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1109\/40.87565"},{"key":"bibr27-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.16"},{"key":"bibr28-1094342015584495","unstructured":"Poss R (2012a) On the realizability of hardware microthreading \u2013 Revisting the general-purpose processor interface: consequences and challenges. Ph.D. thesis, University of Amsterdam, Netherlands, 2012."},{"key":"bibr29-1094342015584495","unstructured":"Poss R (2012b) SL - a \u201cquick and dirty\u201d but working intermediate language for SVP systems. Technical Report, 2012, University of Amsterdam."},{"key":"bibr30-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1145\/2162131.2162134"},{"key":"bibr31-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2013.6621109"},{"key":"bibr32-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2013.05.004"},{"key":"bibr33-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1145\/244804.244807"},{"key":"bibr34-1094342015584495","volume-title":"High-level simulation of the Microgrid","author":"Uddin I","year":"2009"},{"key":"bibr35-1094342015584495","unstructured":"Uddin I (2013a) Design space exploration in the microthreaded many-core architecture. Technical report, University of Amsterdam, 2013."},{"key":"bibr36-1094342015584495","unstructured":"Uddin I (2013b) Microgrid \u2013 the microthreaded many-core architecture. Technical report, University of Amsterdam, 2013."},{"key":"bibr37-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1145\/2162131.2162132"},{"key":"bibr38-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1109\/PDP.2014.81"},{"key":"bibr39-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2014.05.003"},{"key":"bibr40-1094342015584495","doi-asserted-by":"publisher","DOI":"10.5220\/0004982405090516"},{"key":"bibr41-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1142\/S0129626411000308"},{"key":"bibr42-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2008.09.006"},{"key":"bibr43-1094342015584495","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.39"}],"container-title":["The International Journal of High Performance Computing Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.1177\/1094342015584495","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/journals.sagepub.com\/doi\/full-xml\/10.1177\/1094342015584495","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.1177\/1094342015584495","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,4]],"date-time":"2025-03-04T08:59:11Z","timestamp":1741078751000},"score":1,"resource":{"primary":{"URL":"https:\/\/journals.sagepub.com\/doi\/10.1177\/1094342015584495"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,7,28]]},"references-count":43,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2017,3]]}},"alternative-id":["10.1177\/1094342015584495"],"URL":"https:\/\/doi.org\/10.1177\/1094342015584495","relation":{},"ISSN":["1094-3420","1741-2846"],"issn-type":[{"value":"1094-3420","type":"print"},{"value":"1741-2846","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,7,28]]}}}