{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,2]],"date-time":"2026-01-02T07:45:59Z","timestamp":1767339959460,"version":"3.38.0"},"reference-count":30,"publisher":"SAGE Publications","issue":"6","license":[{"start":{"date-parts":[[2019,5,9]],"date-time":"2019-05-09T00:00:00Z","timestamp":1557360000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/journals.sagepub.com\/page\/policies\/text-and-data-mining-license"}],"content-domain":{"domain":["journals.sagepub.com"],"crossmark-restriction":true},"short-container-title":["The International Journal of High Performance Computing Applications"],"published-print":{"date-parts":[[2019,11]]},"abstract":"<jats:p> With the recent advent of many-core architectures such as chip multiprocessors (CMPs), the number of processing units accessing a global shared memory is constantly increasing. Co-scheduling techniques are used to improve application throughput on such architectures, but sharing resources often generates critical interferences. In this article, we focus on the interferences in the last level of cache (LLC) and use the Cache Allocation Technology (CAT) recently provided by Intel to partition the LLC and give each co-scheduled application their own cache area. We consider m iterative HPC applications running concurrently and answer to the following questions: (i) How to precisely model the behavior of these applications on the cache-partitioned platform? and (ii) how many cores and cache fractions should be assigned to each application to maximize the platform efficiency? Here, platform efficiency is defined as maximizing the performance either globally, or as guaranteeing a fixed ratio of iterations per second for each application. Through extensive experiments using CAT, we demonstrate the impact of cache partitioning when multiple HPC applications are co-scheduled onto CMP platforms. <\/jats:p>","DOI":"10.1177\/1094342019846956","type":"journal-article","created":{"date-parts":[[2019,5,10]],"date-time":"2019-05-10T03:16:07Z","timestamp":1557458167000},"page":"1221-1239","update-policy":"https:\/\/doi.org\/10.1177\/sage-journals-update-policy","source":"Crossref","is-referenced-by-count":9,"title":["Co-scheduling HPC workloads on cache-partitioned CMP platforms"],"prefix":"10.1177","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8862-3277","authenticated-orcid":false,"given":"Guillaume","family":"Aupy","sequence":"first","affiliation":[{"name":"Inria, Universit\u00e9 de Bordeaux, France"}]},{"given":"Anne","family":"Benoit","sequence":"additional","affiliation":[{"name":"Laboratoire LIP, \u00c9cole Normale Sup\u00e9rieure de Lyon, France"},{"name":"CSE, Georgia Institute of Technology, Atlanta, USA"}]},{"given":"Brice","family":"Goglin","sequence":"additional","affiliation":[{"name":"Inria, Universit\u00e9 de Bordeaux, France"}]},{"given":"Lo\u00efc","family":"Pottier","sequence":"additional","affiliation":[{"name":"Laboratoire LIP, \u00c9cole Normale Sup\u00e9rieure de Lyon, France"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2361-055X","authenticated-orcid":false,"given":"Yves","family":"Robert","sequence":"additional","affiliation":[{"name":"Laboratoire LIP, \u00c9cole Normale Sup\u00e9rieure de Lyon, France"},{"name":"ICL, University of Tennessee, Knoxville, USA"}]}],"member":"179","published-online":{"date-parts":[[2019,5,9]]},"reference":[{"key":"bibr1-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1145\/1465482.1465560"},{"key":"bibr2-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1177\/1094342017710806"},{"key":"bibr3-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1145\/125826.125925"},{"key":"bibr4-1094342019846956","doi-asserted-by":"crossref","unstructured":"Bao S, Huo Y, Parvathaneni P, et al. (2017) A data colocation grid framework for big data medical image processing-backend design. arXiv preprint arXiv:1712.08634.","DOI":"10.1117\/12.2293694"},{"key":"bibr5-1094342019846956","first-page":"577","volume-title":"Computer Graphics Forum","volume":"35","author":"Bauer AC","year":"2016"},{"key":"bibr6-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1177\/109434200001400303"},{"key":"bibr7-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2008.42"},{"key":"bibr8-1094342019846956","unstructured":"Computing P (2017) Zettascaler-2.0 configurable liquid immersion cooling system. Available at: http:\/\/www.exascaler.co.jp\/wp-content\/uploads\/2017\/11\/zettascaler2.0_en_page.pdf (accessed 29 April 2009)."},{"key":"bibr9-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1109\/CCGrid.2014.92"},{"key":"bibr10-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1145\/1629335.1629369"},{"key":"bibr11-1094342019846956","first-page":"1","volume":"10","author":"Hartstein A","year":"2008","journal-title":"The Journal of Instruction-Level Parallelism"},{"key":"bibr12-1094342019846956","first-page":"111","volume-title":"Proceedings of the 13th international conference on parallel architectures and compilation techniques","author":"Kim S","year":"2004"},{"key":"bibr13-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2012.6189219"},{"key":"bibr14-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1145\/2592798.2592821"},{"key":"bibr15-1094342019846956","first-page":"367","volume-title":"HPCA 2008. IEEE 14th international symposium on high performance computer architecture, 2008","author":"Lin J","year":"2008"},{"key":"bibr16-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1145\/2882783"},{"key":"bibr17-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1145\/2807591.2807656"},{"key":"bibr18-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155664"},{"key":"bibr19-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1145\/1273440.1250671"},{"key":"bibr20-1094342019846956","unstructured":"Nguyen KT (2016) Introduction to Cache Allocation Technology in the Intel\u00ae Xeon\u00ae Processor E5 v4 Family. Available at: https:\/\/software.intel.com\/en-us\/articles\/introduction-to-cache-allocation-technology (accessed 29 April 2019)."},{"key":"bibr21-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"bibr22-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555801"},{"key":"bibr23-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1145\/2807591.2807663"},{"key":"bibr24-1094342019846956","unstructured":"Strohmaier E, et al. (2017) The top500 benchmark. Available at: https:\/\/www.top500.org\/ (accessed 29 April 2019)."},{"key":"bibr25-1094342019846956","unstructured":"Tam D, Azimi R, Soares L, et al. (2007) Managing shared l2 caches on multicore systems in software. In: Workshop on the interaction between operating systems and computer architecture, pp. 26\u201333. Citeseer. Available at: http:\/\/citeseerx.ist.psu.edu\/viewdoc\/download;jsessionid=EB27CBF17D509076312AF3C9AB88BFA8?doi=10.1.1.483.5363&rep=rep1&type=pdf"},{"key":"bibr26-1094342019846956","first-page":"355","volume-title":"Proceedings of the 17th annual international symposium on computer architecture, 1990","author":"Taylor G","year":"1990"},{"key":"bibr27-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1145\/1531743.1531752"},{"key":"bibr28-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.53"},{"key":"bibr29-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1145\/1735971.1736036"},{"key":"bibr30-1094342019846956","doi-asserted-by":"publisher","DOI":"10.1145\/2379776.2379780"}],"container-title":["The International Journal of High Performance Computing Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.1177\/1094342019846956","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/journals.sagepub.com\/doi\/full-xml\/10.1177\/1094342019846956","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.1177\/1094342019846956","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T21:21:31Z","timestamp":1740864091000},"score":1,"resource":{"primary":{"URL":"https:\/\/journals.sagepub.com\/doi\/10.1177\/1094342019846956"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5,9]]},"references-count":30,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2019,11]]}},"alternative-id":["10.1177\/1094342019846956"],"URL":"https:\/\/doi.org\/10.1177\/1094342019846956","relation":{},"ISSN":["1094-3420","1741-2846"],"issn-type":[{"type":"print","value":"1094-3420"},{"type":"electronic","value":"1741-2846"}],"subject":[],"published":{"date-parts":[[2019,5,9]]}}}