{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T21:55:00Z","timestamp":1781906100909,"version":"3.54.5"},"reference-count":626,"publisher":"SAGE Publications","issue":"4","license":[{"start":{"date-parts":[[2025,12,16]],"date-time":"2025-12-16T00:00:00Z","timestamp":1765843200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"},{"start":{"date-parts":[[2025,12,16]],"date-time":"2025-12-16T00:00:00Z","timestamp":1765843200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/journals.sagepub.com\/page\/policies\/text-and-data-mining-license"}],"funder":[{"DOI":"10.13039\/100006584","name":"ExxonMobil Research and Engineering Company","doi-asserted-by":"publisher","award":["EM10480.36"],"award-info":[{"award-number":["EM10480.36"]}],"id":[{"id":"10.13039\/100006584","id-type":"DOI","asserted-by":"publisher"}]},{"name":"National Science Foundation","award":["2326894"],"award-info":[{"award-number":["2326894"]}]},{"name":"National Science Foundation","award":["2425655"],"award-info":[{"award-number":["2425655"]}]},{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["1763848"],"award-info":[{"award-number":["1763848"]}],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["journals.sagepub.com"],"crossmark-restriction":true},"short-container-title":["The International Journal of High Performance Computing Applications"],"published-print":{"date-parts":[[2026,7]]},"abstract":"<jats:p>Computing technology has evolved significantly during the past five decades. As semiconductor scaling is reaching physical and technological limits, it is driving many transformative changes in computing hardware. This has led to computing systems that rely heavily on multi-core processors and GPUs, and resulted in the development of specialized hardware for applications in machine learning and scientific computing. While modern hardware provides significant computing power, and therefore opportunities, it challenges many established algorithms and workflows in scientific computing: these algorithms may not be able to fully leverage modern hardware. Often times, effective use of modern hardware entails revised algorithms, and even rewriting a considerable portion of an existing code. Understanding technology trends in computing hardware is necessary for designing next-generation algorithms for scientific computing. This paper reviews these trends, along with their drivers, in a language that is accessible to computational and data scientists, and applied mathematicians. In this paper (Part I), we review technology evolution in general-purpose microprocessors and hardware accelerators, along with background material. In Part II (Hanindhito et al., 2026), we consider memory systems, inter-device communication, heterogeneous computing and system integration, energy consumption, and how these trends impact scientific computing.<\/jats:p>","DOI":"10.1177\/10943420251348799","type":"journal-article","created":{"date-parts":[[2025,12,16]],"date-time":"2025-12-16T10:44:24Z","timestamp":1765881864000},"page":"558-617","update-policy":"https:\/\/doi.org\/10.1177\/sage-journals-update-policy","source":"Crossref","is-referenced-by-count":2,"title":["Technology trends in computing hardware and their impacts on high-performance scientific computing Part I: General-purpose processors and hardware accelerators"],"prefix":"10.1177","volume":"40","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8485-581X","authenticated-orcid":false,"given":"Bagus","family":"Hanindhito","sequence":"first","affiliation":[{"name":"The University of Texas at Austin"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6809-9815","authenticated-orcid":false,"given":"Arash","family":"Fathi","sequence":"additional","affiliation":[{"name":"ExxonMobil Technology and Engineering Company"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5011-9646","authenticated-orcid":false,"given":"Dimitrios","family":"Gourounas","sequence":"additional","affiliation":[{"name":"The University of Texas at Austin"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dimitar","family":"Trenev","sequence":"additional","affiliation":[{"name":"ExxonMobil Technology and Engineering Company"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Andreas","family":"Gerstlauer","sequence":"additional","affiliation":[{"name":"The University of Texas at Austin"},{"name":"The University of Texas at Austin"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Lizy K","family":"John","sequence":"additional","affiliation":[{"name":"The University of Texas at Austin"},{"name":"The University of Texas at Austin"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"179","published-online":{"date-parts":[[2025,12,16]]},"reference":[{"key":"e_1_3_5_2_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-01759-9_2"},{"key":"e_1_3_5_3_1","unstructured":"Abadi M Agarwal A Barham P et al. (2015) TensorFlow: large-scale machine learning on heterogeneous systems. Software available from tensorflow.org."},{"key":"e_1_3_5_4_1","doi-asserted-by":"crossref","unstructured":"Abdelfattah MS Betz V (2012) Design tradeoffs for hard and soft FPGA-based networks-on-chip. In: 2012 international conference on field-programmable technology Seoul South Korea 10\u201312 December 2012 pp. 95\u2013103.","DOI":"10.1109\/FPT.2012.6412118"},{"key":"e_1_3_5_5_1","doi-asserted-by":"crossref","unstructured":"Abdennadher S Tripician K Singaravelu S (2020) At speed testing challenges and solutions for 56Gbps and 112Gbps PAM4 SerDes. In: 2020 IEEE Latin-American test symposium (LATS) Maceio Brazil 30 March\u20132 April 2020 pp. 1\u20135.","DOI":"10.1109\/LATS49555.2020.9093685"},{"key":"e_1_3_5_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/342001.339691"},{"key":"e_1_3_5_7_1","doi-asserted-by":"crossref","unstructured":"Agarwal R Cheng P Shah P et al. (2022) 3D packaging for heterogeneous integration. In: 2022 IEEE 72nd electronic components and technology conference (ECTC) San Diego California 31 May\u20133 June 2022 pp. 1103\u20131107.","DOI":"10.1109\/ECTC51906.2022.00178"},{"key":"e_1_3_5_8_1","doi-asserted-by":"crossref","unstructured":"Ahmad S Subramanian S Boppana V et al. (2019) Xilinx first 7nm device: Versal AI core (VC1902). In: 2019 IEEE hot chips 31 symposium (HCS) Cupertino CA 18\u201320 August 2019 pp. 1\u201328.","DOI":"10.1109\/HOTCHIPS.2019.8875639"},{"key":"e_1_3_5_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2011.6056626"},{"key":"e_1_3_5_10_1","doi-asserted-by":"crossref","unstructured":"Ahn JH Jouppi NP Kozyrakis C et al. (2009) Future scaling of processor-memory interfaces. In: Proceedings of the conference on high performance computing networking storage and analysis SC \u201909. New York NY: Association for Computing Machinery pp. 1\u201312.","DOI":"10.1145\/1654059.1654102"},{"key":"e_1_3_5_11_1","doi-asserted-by":"crossref","unstructured":"Aktemur B Metzger M Saiapova N et al. (2020) Debugging SYCL programs on heterogeneous Intel\u00ae architectures. In: Proceedings of the international workshop on OpenCL IWOCL \u201920. New York NY: Association for Computing Machinery pp. 1\u201310.","DOI":"10.1145\/3388333.3388646"},{"key":"e_1_3_5_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.73"},{"key":"e_1_3_5_13_1","doi-asserted-by":"crossref","unstructured":"Albina CM Hackl G (2007) Layout parasitic interconnections effects on high frequency circuits. In: 2007 6th IEEE Dallas circuits and systems workshop on system-on-chip Dallas TX 15-16 November 2007 pp. 1\u20134.","DOI":"10.1109\/DCAS.2007.4433202"},{"key":"e_1_3_5_14_1","doi-asserted-by":"crossref","unstructured":"Aleksic S (2017) The future of optical interconnects for data centers: a review of technology trends. In: 2017 14th international conference on telecommunications (ConTEL) Zagreb Croatia 28\u201330 June 2017 pp. 41\u201346.","DOI":"10.23919\/ConTEL.2017.8000037"},{"key":"e_1_3_5_15_1","doi-asserted-by":"crossref","unstructured":"Alexa M Gross M Pauly M et al. (2004) Point-based computer graphics. In: ACM SIGGRAPH 2004 course notes SIGGRAPH \u201904. New York NY: Association for Computing Machinery p. 7.","DOI":"10.1145\/1103900.1103907"},{"key":"e_1_3_5_16_1","doi-asserted-by":"crossref","unstructured":"Altaf MSB Wood DA (2017) LogCA: a high-level performance model for hardware accelerators. In: Proceedings of the 44th annual international symposium on computer architecture ISCA \u201917. New York NY: Association for Computing Machinery pp. 375\u2013388.","DOI":"10.1145\/3079856.3080216"},{"key":"e_1_3_5_17_1","doi-asserted-by":"crossref","unstructured":"Alyaei BR Glass A (2009) Line coded modulation. In: 2009 3rd international conference on signal processing and communication systems Omaha Nebraska 28\u201330 September 2009 pp. 1\u20134.","DOI":"10.1109\/ICSPCS.2009.5306403"},{"key":"e_1_3_5_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSTQE.2009.2013182"},{"key":"e_1_3_5_19_1","volume-title":"Ampere\u00ae Altra\u00ae Max 64-bit Multi-Core Processor Featrures","author":"Ampere Computing LLC","year":"2022","unstructured":"Ampere Computing LLC (2022) Ampere\u00ae Altra\u00ae Max 64-bit Multi-Core Processor Featrures. Whitepaper, Ampere Computing LLC."},{"key":"e_1_3_5_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.910482"},{"key":"e_1_3_5_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2005.862423"},{"key":"e_1_3_5_22_1","doi-asserted-by":"publisher","DOI":"10.1149\/2.F06991IF"},{"key":"e_1_3_5_23_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.425.0567"},{"key":"e_1_3_5_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCG.2011.27"},{"key":"e_1_3_5_25_1","doi-asserted-by":"crossref","unstructured":"Anzt H Tsai YM Abdelfattah A et al. (2020) Evaluating the performance of NVIDIA\u2019s A100 ampere GPU for sparse and batched computations. In: 2020 IEEE\/ACM performance modeling benchmarking and simulation of high performance computer systems (PMBS) Atlanta Georgia 12 November 2020 pp. 26\u201338.","DOI":"10.1109\/PMBS51919.2020.00009"},{"key":"e_1_3_5_26_1","unstructured":"Arcelin B (2021) Comparison of graphcore IPUs and Nvidia GPUs for cosmology applications."},{"key":"e_1_3_5_27_1","doi-asserted-by":"publisher","DOI":"10.1016\/S1359-0286(02)00116-X"},{"key":"e_1_3_5_28_1","doi-asserted-by":"crossref","unstructured":"Arora A Mehta S Betz V et al. (2021) Tensor slices to the rescue: supercharging ML acceleration on FPGAs. In: The 2021 ACM\/SIGDA international symposium on field-programmable gate arrays FPGA \u201921. New York NY: Association for Computing Machinery pp. 23\u201333.","DOI":"10.1145\/3431920.3439282"},{"key":"e_1_3_5_29_1","doi-asserted-by":"crossref","unstructured":"Arora A Anand T Borda A et al. (2022) CoMeFa: compute-in-memory blocks for FPGAs. In: 2022 IEEE 30th annual international symposium on field-programmable custom computing machines (FCCM) New York City NY 15\u201318 May 2022 pp. 1\u20139.","DOI":"10.1109\/FCCM53951.2022.9786179"},{"key":"e_1_3_5_30_1","doi-asserted-by":"crossref","unstructured":"Arunkumar A Bolotin E Cho B et al. (2017) MCM-GPU: multi-chip-module GPUs for continued performance scalability. In: Proceedings of the 44th annual international symposium on computer architecture ISCA \u201917. New York NY: Association for Computing Machinery pp. 320\u2013332.","DOI":"10.1145\/3079856.3080231"},{"key":"e_1_3_5_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/390016.808469"},{"key":"e_1_3_5_32_1","volume-title":"Optical I\/O Chiplets Eliminate Bottlenecks to Unleash Innovation","author":"Ayar Labs Inc","year":"2021","unstructured":"Ayar Labs Inc (2021) Optical I\/O Chiplets Eliminate Bottlenecks to Unleash Innovation. Whitepaper, Ayar Labs Inc."},{"key":"e_1_3_5_33_1","doi-asserted-by":"publisher","DOI":"10.1535\/itj.0904.02"},{"key":"e_1_3_5_34_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.3586773"},{"key":"e_1_3_5_35_1","doi-asserted-by":"crossref","unstructured":"Balasubramanian K Agili S Morales A (2011) Investigating the new 64b\/66b encoding scheme\u2019s power spectral density. In: 2011 IEEE international conference on consumer electronics (ICCE) Las Vegas Nevada 9\u201312 January 2011 pp. 377\u2013378.","DOI":"10.1109\/ICCE.2011.5722636"},{"key":"e_1_3_5_36_1","doi-asserted-by":"crossref","unstructured":"Balewski J Liu Z Tsyplikhin A et al. (2022) Time-series ML-regression on graphcore IPU-M2000 and Nvidia A100. In: 2022 IEEE\/ACM international workshop on performance modeling benchmarking and simulation of high performance computer systems (PMBS) Dallas TX 13\u201318 November 2022 pp. 141\u2013146.","DOI":"10.1109\/PMBS56514.2022.00019"},{"key":"e_1_3_5_37_1","doi-asserted-by":"crossref","unstructured":"Ball T Larus JR (1993) Branch prediction for free. In: Proceedings of the ACM SIGPLAN 1993 conference on programming language design and implementation PLDI \u201993. New York NY: Association for Computing Machinery pp. 300\u2013313.","DOI":"10.1145\/155090.155119"},{"key":"e_1_3_5_38_1","doi-asserted-by":"crossref","unstructured":"Bandyopadhyay J Cases M (2000) Packaging challenges in the design of a 800 Mbps source-synchronous simultaneous bi-directional parallel interface. In: IEEE 9th topical meeting on electrical performance of electronic packaging (Cat. No.00TH8524) Scottsdale AZ 23\u201325 October 2000 pp. 9\u201312.","DOI":"10.1109\/EPEP.2000.895481"},{"key":"e_1_3_5_39_1","doi-asserted-by":"crossref","unstructured":"Barnwell P Wood J (1997) A novel thick film on ceramic MCM technology offering MCM-D performance. In: Proceedings 1997 international conference on multichip modules Santa Cruz CA 4\u20135 February 1997 pp. 48\u201352.","DOI":"10.1109\/ICMCM.1997.581145"},{"key":"e_1_3_5_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/3267934"},{"key":"e_1_3_5_41_1","volume-title":"Semiconductor Design and Manufacturing: Achieving Leading-Edge Capabilities","author":"Bauer H","year":"2020","unstructured":"Bauer H, Burkacky O, Kenevan P, et al. (2020) Semiconductor Design and Manufacturing: Achieving Leading-Edge Capabilities. Report. McKinsey & Company."},{"key":"e_1_3_5_42_1","doi-asserted-by":"crossref","unstructured":"Bays W Lange KD (2012) SPEC: driving better benchmarks. In: Proceedings of the 3rd ACM\/SPEC international conference on performance engineering ICPE \u201912. New York NY: Association for Computing Machinery pp. 249\u2013250.","DOI":"10.1145\/2188286.2188327"},{"key":"e_1_3_5_43_1","doi-asserted-by":"crossref","unstructured":"Beck N White S Paraschou M et al. (2018) \u2018Zeppelin\u2019: an SoC for multichip architectures. In: 2018 IEEE international solid - state circuits conference - (ISSCC) San Francisco CA 11\u201315 February 2018 pp. 40\u201342.","DOI":"10.1109\/ISSCC.2018.8310173"},{"key":"e_1_3_5_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCSE.2009.11"},{"key":"e_1_3_5_45_1","doi-asserted-by":"crossref","unstructured":"Berg T Siegel H (1991) Instruction execution trade-offs for SIMD vs. MIMD vs. mixed mode parallelism. In: [1991] Proceedings. the fifth international parallel processing symposium Anaheim CA 30 April\u201302 May 1991 pp. 301\u2013308.","DOI":"10.1109\/IPPS.1991.153795"},{"key":"e_1_3_5_46_1","unstructured":"Besta M Stanojevic D Licht JDF et al. (2019) Graph processing on FPGAs: taxonomy survey challenges."},{"key":"e_1_3_5_47_1","doi-asserted-by":"crossref","unstructured":"Beyne E (2003) Cu interconnects and low-k dielectrics challenges for chip interconnections and packaging. In: Proceedings of the IEEE 2003 international interconnect technology conference (Cat. No.03TH8695) Burlingame CA 04 June 2003 pp. 221\u2013223.","DOI":"10.1109\/IITC.2003.1219759"},{"key":"e_1_3_5_48_1","doi-asserted-by":"crossref","unstructured":"Beyne E Milojevic D Van der Plas G et al. (2021) 3D SoC integration beyond 2.5D chiplets. In: 2021 IEEE international electron devices meeting (IEDM) San Francisco 11\u201315 December 2021 pp. 3.6.1\u20133.6.4.","DOI":"10.1109\/IEDM19574.2021.9720614"},{"key":"e_1_3_5_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/250015.250016"},{"key":"e_1_3_5_50_1","doi-asserted-by":"crossref","unstructured":"Biswas A (2021) Sapphire rapids. In: 2021 IEEE hot chips 33 symposium (HCS) Palo Alto CA 22\u201324 August 2021 pp. 1\u201322.","DOI":"10.1109\/HCS52781.2021.9566865"},{"key":"e_1_3_5_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/1880018.1880019"},{"key":"e_1_3_5_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2009.934110"},{"key":"e_1_3_5_53_1","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1816000"},{"key":"e_1_3_5_54_1","doi-asserted-by":"crossref","unstructured":"Blem E Menon J Sankaralingam K (2013) Power struggles: revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures. In: 2013 IEEE 19th international symposium on high performance computer architecture (HPCA) Shenzhen China 23\u201327 February 2013 pp. 1\u201312.","DOI":"10.1109\/HPCA.2013.6522302"},{"key":"e_1_3_5_55_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.917718"},{"key":"e_1_3_5_56_1","doi-asserted-by":"publisher","DOI":"10.1002\/lpor.201700237"},{"key":"e_1_3_5_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/MMM.2011.941411"},{"key":"e_1_3_5_58_1","doi-asserted-by":"publisher","DOI":"10.1109\/MMM.2022.3148810"},{"issue":"1","key":"e_1_3_5_59_1","first-page":"7","article-title":"The microarchitecture of the intel pentium 4 processor on 90nm technology","volume":"8","author":"Boggs D","year":"2004","unstructured":"Boggs D, Baktha A, Hawkins J, et al. (2004) The microarchitecture of the intel pentium 4 processor on 90nm technology. Intel Technology Journal 8(1): 7\u201323.","journal-title":"Intel Technology Journal"},{"key":"e_1_3_5_60_1","unstructured":"Bohl S (2022) Graphcore IPUs: accelerating Argonne\u2019s AI\/ML applications. In: Argonne training program on extreme-scale computing (ATPESC) 2022."},{"key":"e_1_3_5_61_1","doi-asserted-by":"publisher","DOI":"10.1109\/N-SSC.2007.4785534"},{"key":"e_1_3_5_62_1","doi-asserted-by":"crossref","unstructured":"Bonilla G Lanzillo N Hu CK et al. (2020) Interconnect scaling challenges and opportunities to enable system-level performance beyond 30 nm pitch. In: 2020 IEEE international electron devices meeting (IEDM) San Francisco 12\u201318 December 2020 pp. 20.4.1\u201320.4.4.","DOI":"10.1109\/IEDM13553.2020.9372093"},{"key":"e_1_3_5_63_1","doi-asserted-by":"crossref","unstructured":"Borkar S (2007) Thousand core chips: a technology perspective. In: Proceedings of the 44th annual design automation conference DAC \u201907. New York NY: Association for Computing Machinery pp. 746\u2013749.","DOI":"10.1145\/1278480.1278667"},{"key":"e_1_3_5_64_1","doi-asserted-by":"publisher","DOI":"10.1145\/3242898"},{"key":"e_1_3_5_65_1","doi-asserted-by":"crossref","unstructured":"Boutros A Nurvitadhi E Ma R et al. (2020) Beyond peak performance: comparing the real performance of AI-optimized FPGAs and GPUs. In: 2020 International conference on field-programmable technology (ICFPT) Maui HI 9\u201311 December 2020 pp. 10\u201319.","DOI":"10.1109\/ICFPT51103.2020.00011"},{"key":"e_1_3_5_66_1","doi-asserted-by":"crossref","unstructured":"Boutros A Arora A Betz V (2024) Field-programmable gate array architecture for deep learning: survey & future directions. arXiv preprint arXiv:2404.10076.","DOI":"10.1007\/978-981-97-9314-3_49"},{"key":"e_1_3_5_67_1","doi-asserted-by":"crossref","unstructured":"Brekelbaum E Rupley J Wilkerson C et al. (2002) Hierarchical scheduling windows. In: 35th Annual IEEE\/ACM international symposium on microarchitecture 2002. (MICRO-35). Proceedings Istanbul Turkey 18\u201322 November 2002 pp. 27\u201336.","DOI":"10.1109\/MICRO.2002.1176236"},{"key":"e_1_3_5_68_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.888701"},{"key":"e_1_3_5_69_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.58"},{"key":"e_1_3_5_70_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-0905-6_39"},{"key":"e_1_3_5_71_1","doi-asserted-by":"crossref","unstructured":"Buck I (2007) GPU computing with NVIDIA CUDA. In: ACM SIGGRAPH 2007 courses SIGGRAPH \u201907. New York NY: Association for Computing Machinery pp. 6\u2013es.","DOI":"10.1145\/1281500.1281647"},{"key":"e_1_3_5_72_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2873584"},{"key":"e_1_3_5_73_1","doi-asserted-by":"crossref","unstructured":"Burd T Li W Pistole J et al. (2022) Zen3: the AMD 2nd-generation 7nm x86-64 microprocessor core. In: 2022 IEEE international solid- state circuits conference (ISSCC) San Francisco CA 20\u201326 February 2022 pp. 1\u20133.","DOI":"10.1109\/ISSCC42614.2022.9731678"},{"key":"e_1_3_5_74_1","doi-asserted-by":"crossref","unstructured":"Burger D Goodman JR K\u00e4gi A (1996) Memory bandwidth limitations of future microprocessors. In: Proceedings of the 23rd annual international symposium on computer architecture ISCA \u201996. New York NY: Association for Computing Machinery pp. 78\u201389.","DOI":"10.1145\/232973.232983"},{"key":"e_1_3_5_75_1","doi-asserted-by":"crossref","unstructured":"Butcher N Olivier SL Berry J et al. (2018) Optimizing for KNL usage modes when data doesn\u2019t fit in MCDRAM. In: Proceedings of the 47th international conference on parallel processing ICPP \u201918. New York NY: Association for Computing Machinery pp. 1\u201310.","DOI":"10.1145\/3225058.3225116"},{"key":"e_1_3_5_76_1","doi-asserted-by":"crossref","unstructured":"Butts J Sohi G (2000) A static power model for architects. In: Proceedings 33rd annual IEEE\/ACM international symposium on microarchitecture. MICRO-33 2000 Monterey CA 10\u201313 December 2000. pp. 191\u2013201.","DOI":"10.1109\/MICRO.2000.898070"},{"key":"e_1_3_5_77_1","doi-asserted-by":"publisher","DOI":"10.1117\/12.591163"},{"key":"e_1_3_5_78_1","unstructured":"Cai Y Fang L Ratemo R et al. (2005) A test case for 3Gbps serial attached SCSI (SAS). In: IEEE international conference on test 2005 Austin TX 8\u201310 November 2005 pp. 9\u2013660."},{"key":"e_1_3_5_79_1","volume-title":"AI Benchmarking on Achronix Speedster\u00ae 7t FPGAs","author":"Cairncross A","year":"2023","unstructured":"Cairncross A, Henry B, Chalmers C, et al. (2023) AI Benchmarking on Achronix Speedster\u00ae 7t FPGAs. White Paper."},{"key":"e_1_3_5_80_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1979.1084691"},{"key":"e_1_3_5_81_1","doi-asserted-by":"crossref","unstructured":"Carter NP Agrawal A Borkar S et al. (2013) Runnemede: an architecture for ubiquitous high-performance computing. In: 2013 IEEE 19th international symposium on high performance computer architecture (HPCA) Shenzhen China 23\u201327 February 2013 pp. 198\u2013209.","DOI":"10.1109\/HPCA.2013.6522319"},{"key":"e_1_3_5_82_1","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2010.2059721"},{"key":"e_1_3_5_83_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2020.9126102"},{"key":"e_1_3_5_84_1","doi-asserted-by":"crossref","unstructured":"Cerebras Systems (2019) Wafer-scale deep learning. In: 2019 IEEE hot chips 31 symposium (HCS) Cupertino CA 18\u201320 August 2019 pp. 1\u201331.","DOI":"10.1109\/HOTCHIPS.2019.8875628"},{"key":"e_1_3_5_85_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF03356749"},{"key":"e_1_3_5_86_1","doi-asserted-by":"publisher","DOI":"10.1109\/101.666591"},{"key":"e_1_3_5_87_1","doi-asserted-by":"crossref","unstructured":"Chang L Tang S King TJ et al. (2000) Gate length scaling and threshold voltage control of double-gate MOSFETs. In: International Electron Devices Meeting 2000. Technical digest. IEDM (Cat. No.00CH37138) pp. 719\u2013722.","DOI":"10.1109\/IEDM.2000.904419"},{"key":"e_1_3_5_88_1","doi-asserted-by":"publisher","DOI":"10.3390\/electronics10040445"},{"key":"e_1_3_5_89_1","doi-asserted-by":"publisher","DOI":"10.1109\/JLT.2023.3311716"},{"key":"e_1_3_5_90_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.912228"},{"key":"e_1_3_5_91_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2008.928529"},{"key":"e_1_3_5_92_1","unstructured":"Chen Z Katopis G (2004) A comparison of performance potentials of single ended vs. differential signaling. In: Electrical performance of electronic packaging - 2004 pp. 185\u2013188."},{"key":"e_1_3_5_93_1","doi-asserted-by":"publisher","DOI":"10.1186\/s43593-021-00002-y"},{"key":"e_1_3_5_94_1","unstructured":"Chen MK Tai CC Huang YJ et al. (2002) Electrical characterization of BGA test socket for high-speed applications. In: Proceedings of the 4th international symposium on electronic materials and packaging 2002 Kaohsiung Taiwan 4\u20136 December 2002 pp. 123\u2013126."},{"key":"e_1_3_5_95_1","doi-asserted-by":"crossref","unstructured":"Chen J Gordon MI Thies W et al. (2005) A reconfigurable architecture for load-balanced rendering. In: Proceedings of the ACM SIGGRAPH\/EUROGRAPHICS conference on graphics hardware HWWS \u201905. New York NY: Association for Computing Machinery pp. 71\u201380.","DOI":"10.1145\/1071866.1071878"},{"key":"e_1_3_5_96_1","doi-asserted-by":"crossref","unstructured":"Chen G Chen H Haurylau M et al. (2006) On-chip copper-based vs. optical interconnects: delay uncertainty latency power and bandwidth density comparative predictions. In: 2006 International interconnect technology conference Burlingame CA 5\u20137 June 2006 pp. 39\u201341.","DOI":"10.1109\/IITC.2006.1648640"},{"key":"e_1_3_5_97_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.carbon.2010.09.021"},{"key":"e_1_3_5_98_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2016.2546246"},{"key":"e_1_3_5_99_1","doi-asserted-by":"crossref","unstructured":"Chen S Hu W Li Z (2019a) High performance data encryption with AES implementation on FPGA. In: 2019 IEEE 5th intl conference on big data security on cloud (BigDataSecurity) IEEE intl conference on high performance and smart computing (HPSC) and IEEE intl conference on intelligent data and security (IDS) pp. 149\u2013153.","DOI":"10.1109\/BigDataSecurity-HPSC-IDS.2019.00036"},{"key":"e_1_3_5_100_1","doi-asserted-by":"crossref","unstructured":"Chen Y He J Zhang X et al. (2019b) Cloud-DNN: an open framework for mapping DNN models to cloud FPGAs. In: Proceedings of the 2019 ACM\/SIGDA international symposium on field-programmable gate arrays FPGA \u201919. New York NY: Association for Computing Machinery pp. 73\u201382.","DOI":"10.1145\/3289602.3293915"},{"key":"e_1_3_5_101_1","doi-asserted-by":"crossref","unstructured":"Chen SS Tajali A Holden B et al. (2023) Noise performance comparison: ENRZ NRZ PAM3 and PAM4. In: 2023 IEEE symposium on electromagnetic compatibility & signal\/power integrity (EMC+SIPI) Grand Rapids MI 31 July\u20134 August 2023 pp. 275\u2013279.","DOI":"10.1109\/EMCSIPI50001.2023.10241458"},{"key":"e_1_3_5_102_1","doi-asserted-by":"crossref","unstructured":"Cheng W Tan Z Gao X et al. (2008) High speed serial interface & some key technology research. In: 2008 International symposium on electronic commerce and security Guangzhou China 3\u20135 August 2008 pp. 562\u2013566.","DOI":"10.1109\/ISECS.2008.105"},{"key":"e_1_3_5_103_1","doi-asserted-by":"crossref","unstructured":"Cheng H Gao J Wu HC et al. (2016) Optics vs. copper \u2014 from the perspective of Thunderbolt 3 interconnect technology. In: 2016 China semiconductor technology international conference (CSTIC) Shanghai China 13\u201314 March 2016 pp. 1\u20133.","DOI":"10.1109\/CSTIC.2016.7464086"},{"key":"e_1_3_5_104_1","doi-asserted-by":"crossref","unstructured":"Chin SA Sakamoto N Rui A et al. (2017) CGRA-ME: a unified framework for CGRA modelling and exploration. In: 2017 IEEE 28th international conference on application-specific systems architectures and processors (ASAP) Seattle WA 10\u201312 July 2017 pp. 184\u2013189.","DOI":"10.1109\/ASAP.2017.7995277"},{"key":"e_1_3_5_105_1","doi-asserted-by":"crossref","unstructured":"Chirkov G Wentzlaff D (2023) Seizing the bandwidth scaling of on-package interconnect in a post-Moore\u2019s law world. In: Proceedings of the 37th ACM international conference on supercomputing ICS \u201923. New York NY: Association for Computing Machinery pp. 410\u2013422.","DOI":"10.1145\/3577193.3593702"},{"key":"e_1_3_5_106_1","doi-asserted-by":"crossref","unstructured":"Cho H Koo KH Kapur P et al. (2007) The delay energy and bandwidth comparisons between copper carbon nanotube and optical interconnects for local and global wiring application. In: 2007 IEEE international interconnect technology conference Burlingame CA 3\u20136 June 2007 pp. 135\u2013137.","DOI":"10.1109\/IITC.2007.382375"},{"key":"e_1_3_5_107_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2007.911617"},{"key":"e_1_3_5_108_1","doi-asserted-by":"crossref","unstructured":"Cho SJ Ahn J Choi H et al. (2012) Performance analysis of multi-bank DRAM with increased clock frequency. In: 2012 IEEE international symposium on circuits and systems (ISCAS) Seoul South Korea 20\u201323 May 2012 pp. 2477\u20132480.","DOI":"10.1109\/ISCAS.2012.6271802"},{"key":"e_1_3_5_109_1","doi-asserted-by":"crossref","unstructured":"Choi K Soma R Pedram M (2004) Dynamic voltage and frequency scaling based on workload decomposition. In: Proceedings of the 2004 international symposium on low power electronics and design ISLPED \u201904. New York NY: Association for Computing Machinery pp. 174\u2013179.","DOI":"10.1145\/1013235.1013282"},{"key":"e_1_3_5_110_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2013.2294466"},{"key":"e_1_3_5_111_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2021.3061394"},{"key":"e_1_3_5_112_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAPT.2006.885959"},{"key":"e_1_3_5_113_1","doi-asserted-by":"crossref","unstructured":"Chrysos G (2012) Intel\u00ae Xeon Phi coprocessor (codename Knights Corner). In: 2012 IEEE hot chips 24 symposium (HCS) Cupertino CA 27\u201329 August 2012 pp. 1\u201331.","DOI":"10.1109\/HOTCHIPS.2012.7476487"},{"key":"e_1_3_5_114_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2013.6685768"},{"key":"e_1_3_5_115_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2554561"},{"key":"e_1_3_5_116_1","doi-asserted-by":"crossref","unstructured":"Cochran R Hankendi C Coskun AK et al. (2011) Pack & cap: adaptive DVFS and thread packing under power caps. In: Proceedings of the 44th annual IEEE\/ACM international symposium on microarchitecture MICRO-44. New York NY: Association for Computing Machinery pp. 175\u2013185.","DOI":"10.1145\/2155620.2155641"},{"key":"e_1_3_5_117_1","doi-asserted-by":"crossref","unstructured":"Cong J Huang M Pan P et al. (2016) Software infrastructure for enabling FPGA-based accelerations in data centers: invited paper. In: Proceedings of the 2016 international symposium on low power electronics and design ISLPED \u201916. New York NY: Association for Computing Machinery pp. 154\u2013155.","DOI":"10.1145\/2934583.2953984"},{"key":"e_1_3_5_118_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.466.0763"},{"key":"e_1_3_5_119_1","volume-title":"Modern Communication Systems","author":"Couch LW","year":"1994","unstructured":"Couch LW (1994) Modern Communication Systems. Macmillan."},{"key":"e_1_3_5_120_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.46766"},{"key":"e_1_3_5_121_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.53"},{"key":"e_1_3_5_122_1","doi-asserted-by":"crossref","unstructured":"Cui Y Ingalz C Gao T et al. (2017) Total cost of ownership model for data center technology evaluation. In: 2017 16th IEEE intersociety conference on thermal and thermomechanical phenomena in electronic systems (ITherm) Orlando FL 30 May\u20132 June 2017 pp. 936\u2013942.","DOI":"10.1109\/ITHERM.2017.7992587"},{"key":"e_1_3_5_123_1","doi-asserted-by":"crossref","unstructured":"Cunningham D (2001) The status of the 10-Gigabit ethernet standard. In: Proceedings 27th European conference on optical communication (Cat. No.01TH8551) Vol. 3 pp. 364\u2013367.","DOI":"10.1109\/ECOC.2001.989668"},{"key":"e_1_3_5_124_1","doi-asserted-by":"publisher","DOI":"10.1007\/s12274-016-1275-7"},{"key":"e_1_3_5_125_1","doi-asserted-by":"publisher","DOI":"10.1145\/3361682"},{"key":"e_1_3_5_126_1","doi-asserted-by":"publisher","DOI":"10.1145\/2133806.2133822"},{"key":"e_1_3_5_127_1","doi-asserted-by":"publisher","DOI":"10.1145\/2181796.2181798"},{"key":"e_1_3_5_128_1","doi-asserted-by":"crossref","unstructured":"Davidson J Jinturkar S (1995) Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation. In: Proceedings of the 28th annual international symposium on microarchitecture Ann Arbor MI 29 November\u20131 December 1995 pp. 125\u2013132.","DOI":"10.1109\/MICRO.1995.476820"},{"key":"e_1_3_5_129_1","first-page":"1","volume-title":"6 Serial Peripheral Interface (SPI)","author":"Dawoud DS","year":"2020","unstructured":"Dawoud DS, Dawoud P (2020) 6 Serial Peripheral Interface (SPI). Chapter 1. River Publishers, pp. 1\u201344."},{"key":"e_1_3_5_130_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2017.34"},{"key":"e_1_3_5_131_1","doi-asserted-by":"crossref","unstructured":"Deepaksubramanyan BS Nunez A (2007) Analysis of subthreshold leakage reduction in CMOS digital circuits. In: 2007 50th midwest symposium on circuits and systems Montreal Canada 5\u20138 August 2007 pp. 1400\u20131404.","DOI":"10.1109\/MWSCAS.2007.4488809"},{"key":"e_1_3_5_132_1","doi-asserted-by":"publisher","DOI":"10.1145\/378456.378468"},{"key":"e_1_3_5_133_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050511"},{"key":"e_1_3_5_134_1","doi-asserted-by":"crossref","unstructured":"Dikhaminjia N He J Tsiklauri M et al. (2016) PAM4 signaling considerations for high-speed serial links. In: 2016 IEEE international symposium on electromagnetic compatibility (EMC) Ottawa ON 25\u201329 July 2016 pp. 906\u2013910.","DOI":"10.1109\/ISEMC.2016.7571771"},{"key":"e_1_3_5_135_1","doi-asserted-by":"crossref","unstructured":"Domke J Matsumura K Wahib M et al. (2019) Double-precision FPUs in high-performance computing: an embarrassment of riches? In: 2019 IEEE international parallel and distributed processing symposium (IPDPS) Rio de Janeiro Brazil 20\u201324 May 2019 pp. 78\u201388.","DOI":"10.1109\/IPDPS.2019.00019"},{"key":"e_1_3_5_136_1","unstructured":"Duan C Tirumala A Khatri S (2001) Analysis and avoidance of cross-talk in on-chip buses. In: HOT 9 interconnects. symposium on high performance interconnects Stanford CA 22\u201324 August 2001 pp. 133\u2013138."},{"key":"e_1_3_5_137_1","first-page":"17","volume-title":"Hardware Description Language: Verilog","author":"Dubey R","year":"2009","unstructured":"Dubey R (2009) Hardware Description Language: Verilog. Chapter 2. Springer, pp. 17\u201351."},{"key":"e_1_3_5_138_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCSE.2015.40"},{"key":"e_1_3_5_139_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.diamond.2003.10.021"},{"key":"e_1_3_5_140_1","doi-asserted-by":"publisher","DOI":"10.1145\/306225.306228"},{"key":"e_1_3_5_141_1","doi-asserted-by":"crossref","unstructured":"Duran A Klemm M (2012) The Intel\u00ae many integrated core architecture. In: 2012 International conference on high performance computing & simulation (HPCS) Madrid Spain 2\u20136 July 2012 pp. 365\u2013366.","DOI":"10.1109\/HPCSim.2012.6266938"},{"key":"e_1_3_5_142_1","doi-asserted-by":"crossref","unstructured":"Dysart T Moore B Schaelicke L et al. (2004) Cache implications of aggressively pipelined high performance microprocessors. In: IEEE international symposium on - ISPASS performance analysis of systems and software 2004 Austin TX 10\u201312 March 2004 pp. 123\u2013132.","DOI":"10.1109\/ISPASS.2004.1291364"},{"key":"e_1_3_5_143_1","first-page":"435","volume-title":"Reconfigurable Architectures: The Shift from General Systems to Domain Specific Solutions","author":"D\u2019Arnese E","year":"2023","unstructured":"D\u2019Arnese E, Conficconi D, Santambrogio MD, et al. (2023) Reconfigurable Architectures: The Shift from General Systems to Domain Specific Solutions. Chapter 5. Springer Nature Singapore, pp. 435\u2013456."},{"key":"e_1_3_5_144_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997879"},{"key":"e_1_3_5_145_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.394.0383"},{"key":"e_1_3_5_146_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.621209"},{"key":"e_1_3_5_147_1","doi-asserted-by":"publisher","DOI":"10.1889\/1.1832462"},{"key":"e_1_3_5_148_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2005.1550165"},{"key":"e_1_3_5_149_1","doi-asserted-by":"crossref","unstructured":"Elliott C (2004) Programming graphics processors functionally. In: Proceedings of the 2004 ACM SIGPLAN workshop on Haskell Haskell \u201904. New York NY: Association for Computing Machinery pp. 45\u201356.","DOI":"10.1145\/1017472.1017482"},{"key":"e_1_3_5_150_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCSE.2021.3057203"},{"key":"e_1_3_5_151_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.413.0215"},{"key":"e_1_3_5_152_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024723.2000108"},{"key":"e_1_3_5_153_1","doi-asserted-by":"crossref","unstructured":"Esmaeilzadeh H Blem E St Amant R et al. (2011b) Dark silicon and the end of multicore scaling. In: Proceedings of the 38th annual international symposium on computer architecture ISCA \u201911. New York NY: Association for Computing Machinery pp. 365\u2013376.","DOI":"10.1145\/2000064.2000108"},{"key":"e_1_3_5_154_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.621210"},{"key":"e_1_3_5_155_1","doi-asserted-by":"crossref","unstructured":"Evans J (2022) Nvidia grace. In: 2022 IEEE hot chips 34 symposium (HCS). Los Alamitos CA: IEEE Computer Society pp. 1\u201320.","DOI":"10.1109\/HCS55958.2022.9895599"},{"key":"e_1_3_5_156_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2022.3152788"},{"key":"e_1_3_5_157_1","doi-asserted-by":"publisher","DOI":"10.1145\/1534909.1534910"},{"key":"e_1_3_5_158_1","doi-asserted-by":"publisher","DOI":"10.1109\/26.76466"},{"key":"e_1_3_5_159_1","doi-asserted-by":"crossref","unstructured":"Fang J Sips H Zhang L et al. (2014) Test-driving Intel Xeon Phi. In: Proceedings of the 5th ACM\/SPEC international conference on performance engineering ICPE \u201914. New York NY: Association for Computing Machinery pp. 137\u2013148.","DOI":"10.1145\/2568088.2576799"},{"key":"e_1_3_5_160_1","doi-asserted-by":"publisher","DOI":"10.1088\/1742-6596\/898\/4\/042012"},{"key":"e_1_3_5_161_1","doi-asserted-by":"crossref","unstructured":"Fawcett B (1995) Designing PCI bus interfaces with programmable logic. In: Proceedings of eighth international application specific integrated circuits conference 321\u2013324.","DOI":"10.1109\/ASIC.1995.580740"},{"key":"e_1_3_5_162_1","doi-asserted-by":"crossref","unstructured":"Firoozshahian A Coburn J Levenstein R et al. (2023) MTIA: first generation silicon targeting meta\u2019s recommendation systems. In: Proceedings of the 50th annual international symposium on computer architecture ISCA \u201923. New York NY: Association for Computing Machinery pp. 1\u201313.","DOI":"10.1145\/3579371.3589348"},{"key":"e_1_3_5_163_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1966.5273"},{"key":"e_1_3_5_164_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1972.5009071"},{"key":"e_1_3_5_165_1","doi-asserted-by":"publisher","DOI":"10.1145\/234313.234345"},{"key":"e_1_3_5_166_1","doi-asserted-by":"crossref","unstructured":"Forghani M Razavi B (2022) Circuit bandwidth requirements for NRZ and PAM4 signals. In: 2022 IEEE international symposium on circuits and systems (ISCAS) Austin TX 27 May\u20131 June 2022 pp. 990\u2013994.","DOI":"10.1109\/ISCAS48785.2022.9937588"},{"key":"e_1_3_5_167_1","unstructured":"Foss R (1997) Taking DRAM from 4 MBytes\/s to 4 GBytes\/s. In: Proceedings of the 23rd European solid-state circuits conference Southampton UK 16\u201318 September 1997 p. 2."},{"key":"e_1_3_5_168_1","doi-asserted-by":"publisher","DOI":"10.1109\/65.690946"},{"key":"e_1_3_5_169_1","volume-title":"Principles of Electronic Communication Systems","author":"Frenzel L","year":"2007","unstructured":"Frenzel L (2007) Principles of Electronic Communication Systems. 3 edition. McGraw-Hill, Inc.","edition":"3"},{"key":"e_1_3_5_170_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.929649"},{"key":"e_1_3_5_171_1","unstructured":"Fritz F (2019a) Amd 12nm zen+ pinnacle ridge die shot."},{"key":"e_1_3_5_172_1","unstructured":"Fritz F (2019b) Amd 7nm ccd and 12nm iod zen2 rome epyc 7702 die shot."},{"key":"e_1_3_5_173_1","unstructured":"Fritz F (2020) Amd 7nm ccd and 12nm iod zen3 vermeer die shot."},{"key":"e_1_3_5_174_1","doi-asserted-by":"crossref","unstructured":"Fu X Zhang Z Fan H et al. (2024) Distributed training of large language lodels on AWS trainium. In: Proceedings of the 2024 ACM symposium on cloud computing Redmond WA 20\u201322 November 2024 pp. 961\u2013976.","DOI":"10.1145\/3698038.3698535"},{"key":"e_1_3_5_175_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-01772-8_6"},{"key":"e_1_3_5_176_1","doi-asserted-by":"crossref","unstructured":"Fujimori I (2014) Evolution of multi-gigabit wireline transceivers in CMOS. In: 2014 IEEE compound semiconductor integrated circuit symposium (CSICS) pp. 1\u20134.","DOI":"10.1109\/CSICS.2014.6978553"},{"key":"e_1_3_5_177_1","doi-asserted-by":"crossref","unstructured":"Fung WWL Aamodt TM (2011) Thread block compaction for efficient SIMT control flow. In: 2011 IEEE 17th international symposium on high performance computer architecture San Antonio TX 12\u201316 February 2011 pp. 25\u201336.","DOI":"10.1109\/HPCA.2011.5749714"},{"key":"e_1_3_5_178_1","doi-asserted-by":"crossref","unstructured":"Gallet B Gowanlock M (2022) Leveraging GPU tensor cores for double precision Euclidean distance calculations. In: 2022 IEEE 29th international conference on high performance computing data and analytics (HiPC). Los Alamitos CA: IEEE Computer Society pp. 135\u2013144.","DOI":"10.1109\/HiPC56025.2022.00029"},{"key":"e_1_3_5_179_1","doi-asserted-by":"crossref","unstructured":"Ganapathy D Warner EJ (2008) Defining thermal design power based on real-world usage models. In: 2008 11th Intersociety conference on thermal and thermomechanical phenomena in electronic systems Orlando FL 28\u201331 May 2008 pp. 1242\u20131246.","DOI":"10.1109\/ITHERM.2008.4544402"},{"key":"e_1_3_5_180_1","doi-asserted-by":"crossref","unstructured":"Gandhare S Karthikeyan B (2019) Survey on FPGA architecture and recent applications. In: 2019 International conference on vision towards emerging trends in communication and networking (Vitecon) pp. 1\u20134.","DOI":"10.1109\/ViTECoN.2019.8899550"},{"key":"e_1_3_5_181_1","doi-asserted-by":"crossref","unstructured":"Gandhi A Akkary H Srinivasan S (2004) Reducing branch misprediction penalty via selective branch recovery. In: 10th International symposium on high performance computer architecture (HPCA\u201904) pp. 254\u2013264.","DOI":"10.1109\/HPCA.2004.10004"},{"key":"e_1_3_5_182_1","doi-asserted-by":"crossref","unstructured":"Gao M Kozyrakis C (2016) HRL: efficient and flexible reconfigurable logic for near-data processing. In: 2016 IEEE international symposium on high performance computer architecture (HPCA) pp. 126\u2013137.","DOI":"10.1109\/HPCA.2016.7446059"},{"key":"e_1_3_5_183_1","doi-asserted-by":"publisher","DOI":"10.3390\/s20020462"},{"key":"e_1_3_5_184_1","doi-asserted-by":"crossref","unstructured":"Garcia JC Montiel-Nelson JA Nooshabadi S (2007) Adaptive low\/high voltage swing CMOS driver for on-chip interconnects. In: 2007 IEEE International symposium on circuits and systems (ISCAS) pp. 881\u2013884.","DOI":"10.1109\/ISCAS.2007.378047"},{"key":"e_1_3_5_185_1","doi-asserted-by":"publisher","DOI":"10.1109\/101.994854"},{"key":"e_1_3_5_186_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCSE.2017.32"},{"key":"e_1_3_5_187_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.160"},{"key":"e_1_3_5_188_1","doi-asserted-by":"publisher","DOI":"10.1557\/S0883769400047734"},{"key":"e_1_3_5_189_1","doi-asserted-by":"publisher","DOI":"10.1117\/12.250884"},{"key":"e_1_3_5_190_1","doi-asserted-by":"crossref","unstructured":"Gelsinger P (2001) Microprocessors for the new millennium: challenges opportunities and new frontiers. In: 2001 IEEE international solid-state circuits conference. Digest of technical papers. ISSCC (Cat. No.01CH37177) pp. 22\u201325.","DOI":"10.1109\/ISSCC.2001.912412"},{"key":"e_1_3_5_191_1","doi-asserted-by":"crossref","unstructured":"Gelsinger P (2022) Semiconductors run the world: hot chips 2022. In: 2022 IEEE hot chips 34 symposium (HCS) pp. 1\u201319.","DOI":"10.1109\/HCS55958.2022.9895614"},{"key":"e_1_3_5_192_1","doi-asserted-by":"crossref","unstructured":"Geng T Wu C Tan C et al. (2020) CQNN: a CGRA-based QNN framework. In: 2020 IEEE high performance extreme computing conference (HPEC) pp. 1\u20137.","DOI":"10.1109\/HPEC43674.2020.9286194"},{"key":"e_1_3_5_193_1","doi-asserted-by":"crossref","unstructured":"Georganas E Avancha S Banerjee K et al. (2018) Anatomy of high-performance deep learning convolutions on SIMD architectures. In: SC18: International conference for high performance computing networking storage and analysis pp. 830\u2013841.","DOI":"10.1109\/SC.2018.00069"},{"key":"e_1_3_5_194_1","doi-asserted-by":"crossref","unstructured":"Gepner P Kowalik M (2006) Multi-core processors: new way to achieve high system performance. In: International symposium on parallel computing in electrical engineering (PARELEC\u201906) pp. 9\u201313.","DOI":"10.1109\/PARELEC.2006.54"},{"key":"e_1_3_5_195_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2002.1038566"},{"key":"e_1_3_5_196_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-1389-6_14"},{"key":"e_1_3_5_197_1","doi-asserted-by":"publisher","DOI":"10.1098\/rsta.2013.0319"},{"key":"e_1_3_5_198_1","doi-asserted-by":"crossref","unstructured":"Gindin R Cidon I Keidar I (2007) NoC-Based FPGA: architecture and routing. In: First international symposium on networks-on-chip (NOCS\u201907) pp. 253\u2013264.","DOI":"10.1109\/NOCS.2007.31"},{"key":"e_1_3_5_199_1","doi-asserted-by":"crossref","unstructured":"Giuma T Hart K (1996) Microcomputer bus architectures. In: Southcon\/96 conference record pp. 431\u2013437.","DOI":"10.1109\/SOUTHC.1996.535106"},{"key":"e_1_3_5_200_1","volume-title":"3D Chips Break Megatriangle Barrier: Better Designs and Processes Help Crank Out 1M Polygons\/s in Mainstream PCs","author":"Glaskowsky P","year":"1997","unstructured":"Glaskowsky P (1997) 3D Chips Break Megatriangle Barrier: Better Designs and Processes Help Crank Out 1M Polygons\/s in Mainstream PCs. Technical report, Microprocessor Report."},{"key":"e_1_3_5_201_1","doi-asserted-by":"crossref","unstructured":"Gohel T (2012) The practical realities of high-speed digital test in a production environment. In: 2012 IEEE AUTOTESTCON proceedings pp. 272\u2013277.","DOI":"10.1109\/AUTEST.2012.6334569"},{"key":"e_1_3_5_202_1","doi-asserted-by":"crossref","unstructured":"Gomes W Khushu S Ingerly DB et al. (2020) 8.1 lakefield and mobility compute: a 3D stacked 10nm and 22FFL hybrid processor system in 12\u00d7 12mm2 1mm package-on-package. In: 2020 IEEE international solid- state circuits conference - (ISSCC) pp. 144\u2013146.","DOI":"10.1109\/ISSCC19947.2020.9062957"},{"key":"e_1_3_5_203_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.535411"},{"key":"e_1_3_5_204_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCG.2005.101"},{"key":"e_1_3_5_205_1","first-page":"31","volume-title":"Packaging the IC\u2014Single Chip Packaging","author":"Greig WJ","year":"2007","unstructured":"Greig WJ (2007) Packaging the IC\u2014Single Chip Packaging. Chapter 3. Springer US, pp. 31\u201345."},{"key":"e_1_3_5_206_1","doi-asserted-by":"crossref","unstructured":"Grelck C Sarris N (2017) Towards compiling SAC for the Xeon Phi Knights Corner and Knights Landing architectures: strategies and experiments. In: Proceedings of the 29th symposium on the implementation and application of functional programming languages IFL \u201917. New York NY: Association for Computing Machinery pp. 1\u201312.","DOI":"10.1145\/3205368.3205377"},{"key":"e_1_3_5_207_1","doi-asserted-by":"crossref","unstructured":"Gribok S Pasca B (2024) Efficient 8-bit matrix multiplication on Intel Agilex-5 FPGAs. In: 2024 IEEE 32nd annual international symposium on field-programmable custom computing machines (FCCM) pp. 43\u201353.","DOI":"10.1109\/FCCM60383.2024.00016"},{"key":"e_1_3_5_208_1","volume-title":"Serial ATA Storage Architecture and Applications: Designing High-Performance, Cost-Effective I\/O Solutions","author":"Grimsrud K","year":"2003","unstructured":"Grimsrud K, Smith H (2003) Serial ATA Storage Architecture and Applications: Designing High-Performance, Cost-Effective I\/O Solutions. Intel Press."},{"key":"e_1_3_5_209_1","doi-asserted-by":"crossref","unstructured":"Groeneveld P James M Kibardin V et al. (2021) ISPD 2021 wafer-scale physics modeling contest: a new frontier for partitioning placement and routing. In: Proceedings of the 2021 international symposium on physical design ISPD \u201921. New York NY: Association for Computing Machinery pp. 143\u2013147.","DOI":"10.1145\/3439706.3446904"},{"key":"e_1_3_5_210_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.668981"},{"key":"e_1_3_5_211_1","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.6261"},{"key":"e_1_3_5_212_1","doi-asserted-by":"crossref","unstructured":"Guri M Monitz M Mirski Y et al. (2015) BitWhisper: covert signaling channel between air-gapped computers using thermal manipulations. In: 2015 IEEE 28th computer security foundations symposium pp. 276\u2013289.","DOI":"10.1109\/CSF.2015.26"},{"key":"e_1_3_5_213_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2004.840160"},{"key":"e_1_3_5_214_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-28869-2_16"},{"key":"e_1_3_5_215_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-9317(00)00499-8"},{"key":"e_1_3_5_216_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-34233-2_1"},{"key":"e_1_3_5_217_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4302-3537-8_8"},{"key":"e_1_3_5_218_1","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815968"},{"key":"e_1_3_5_219_1","doi-asserted-by":"crossref","unstructured":"Hameed R Qadeer W Wachs M et al. (2010b) Understanding sources of inefficiency in general-purpose chips. In: Proceedings of the 37th annual international symposium on computer architecture ISCA \u201910. New York NY: Association for Computing Machinery pp. 37\u201347.","DOI":"10.1145\/1815961.1815968"},{"key":"e_1_3_5_220_1","doi-asserted-by":"publisher","DOI":"10.1109\/30.536154"},{"key":"e_1_3_5_221_1","first-page":"109434202513474","article-title":"Technology trends in computing hardware and their impacts on high-performance scientific computing Part II: memory systems, interconnects, and system integration","author":"Hanindhito B","year":"2026","unstructured":"Hanindhito B, Fathi A, Gourounas D, et al. (2026) Technology trends in computing hardware and their impacts on high-performance scientific computing Part II: memory systems, interconnects, and system integration. The International Journal of High Performance Computing Applications: 10943420251347461.","journal-title":"The International Journal of High Performance Computing Applications"},{"key":"e_1_3_5_222_1","doi-asserted-by":"publisher","DOI":"10.1109\/LPT.2021.3084945"},{"key":"e_1_3_5_223_1","doi-asserted-by":"publisher","DOI":"10.1166\/jnn.2008.207"},{"key":"e_1_3_5_224_1","doi-asserted-by":"crossref","unstructured":"Harrand M Henry M Chaisemartin P et al. (1995) A single chip videophone video encoder\/decoder. In: Proceedings ISSCC \u201995 - international solid-state circuits conference pp. 292\u2013293.","DOI":"10.1109\/ISSCC.1995.535561"},{"key":"e_1_3_5_225_1","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/bxm099"},{"key":"e_1_3_5_226_1","unstructured":"Hawick KA Playne DP (2014) Developmental directions in parallel accelerators. In: Proceedings of the twelfth Australasian symposium on parallel and distributed computing - Volume 152 AusPDC \u201914. AUS: Australian Computer Society Inc. pp. 21\u201327."},{"key":"e_1_3_5_227_1","doi-asserted-by":"crossref","unstructured":"He X Chen Z Sun J et al. (2017) Exploring synchronization in cache coherent manycore systems: a case study with Xeon Phi. In: 2017 IEEE 23rd international conference on parallel and distributed systems (ICPADS) pp. 232\u2013239.","DOI":"10.1109\/ICPADS.2017.00040"},{"key":"e_1_3_5_228_1","doi-asserted-by":"crossref","unstructured":"Hecht U Wittenhagen E Cirit H et al. (2022) PAM-4\/6\/8 performance and power analysis for next generation 224Gbit\/s links. In: 2022 IEEE international symposium on circuits and systems (ISCAS) pp. 752\u2013756.","DOI":"10.1109\/ISCAS48785.2022.9937895"},{"key":"e_1_3_5_229_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCSE.2012.23"},{"key":"e_1_3_5_230_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2021.3112301"},{"key":"e_1_3_5_231_1","doi-asserted-by":"publisher","DOI":"10.1145\/3282307"},{"key":"e_1_3_5_232_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.869367"},{"key":"e_1_3_5_233_1","doi-asserted-by":"crossref","unstructured":"Herbert S Marculescu D (2007) Analysis of dynamic voltage\/frequency scaling in chip-multiprocessors. In: Proceedings of the 2007 international symposium on low power electronics and design ISLPED \u201907. New York NY: Association for Computing Machinery pp. 38\u201343.","DOI":"10.1145\/1283780.1283790"},{"key":"e_1_3_5_234_1","doi-asserted-by":"publisher","DOI":"10.1145\/3460970"},{"key":"e_1_3_5_235_1","unstructured":"Hitachi Ltd (1997) Hitachi releases the 125 MHz 8M-Bit synchronous graphic RAM."},{"key":"e_1_3_5_236_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"e_1_3_5_237_1","doi-asserted-by":"crossref","unstructured":"Holzinger P Reiser D Hahn T et al. (2021) Fast HBM access with FPGAs: analysis architectures and applications. In: 2021 IEEE international parallel and distributed processing symposium workshops (IPDPSW) pp. 152\u2013159.","DOI":"10.1109\/IPDPSW52791.2021.00030"},{"key":"e_1_3_5_238_1","doi-asserted-by":"crossref","unstructured":"Hood R Jin H Mehrotra P et al. (2010) Performance impact of resource contention in multicore systems. In: 2010 IEEE international symposium on parallel & distributed processing (IPDPS) pp. 1\u201312.","DOI":"10.1109\/IPDPS.2010.5470399"},{"key":"e_1_3_5_239_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2021.3071608"},{"key":"e_1_3_5_240_1","doi-asserted-by":"crossref","unstructured":"Horowitz M (2014) 1.1 Computing\u2019s energy problem (and what we can do about it). In: 2014 IEEE international solid-state circuits conference digest of technical papers (ISSCC) pp. 10\u201314.","DOI":"10.1109\/ISSCC.2014.6757323"},{"key":"e_1_3_5_241_1","unstructured":"Horowitz M Labonte F Shacham O et al. (2015) 35 Years of microprocessor trend data."},{"key":"e_1_3_5_242_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-40843-4_48"},{"key":"e_1_3_5_243_1","unstructured":"Hruska J (2018) As chip design costs skyrocket 3nm process node is in Jeopardy."},{"key":"e_1_3_5_244_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2002655"},{"key":"e_1_3_5_245_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.3169265"},{"key":"e_1_3_5_246_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.011441561"},{"key":"e_1_3_5_247_1","doi-asserted-by":"crossref","unstructured":"Hu Y Du Y Ustun E et al. (2021) GraphLily: accelerating graph linear algebra on HBM-equipped FPGAs. In: 2021 IEEE\/ACM international conference on computer aided design (ICCAD) pp. 1\u20139.","DOI":"10.1109\/ICCAD51958.2021.9643582"},{"key":"e_1_3_5_248_1","doi-asserted-by":"crossref","unstructured":"Huang CY Yin YF Hsu CJ et al. (2011) SoC HW\/SW verification and validation. In: 16th Asia and South Pacific design automation conference (ASP-DAC 2011) pp. 297\u2013300.","DOI":"10.1109\/ASPDAC.2011.5722202"},{"key":"e_1_3_5_249_1","doi-asserted-by":"crossref","unstructured":"Huang Y Guo N Seok M et al. (2017) Hybrid analog-digital solution of nonlinear partial differential equations. In: Proceedings of the 50th annual IEEE\/ACM international symposium on microarchitecture MICRO-50 \u201917. New York NY: Association for Computing Machinery pp. 665\u2013678.","DOI":"10.1145\/3123939.3124550"},{"key":"e_1_3_5_250_1","doi-asserted-by":"crossref","unstructured":"Huang V Shim D Simka H et al. (2020) From interconnect materials and processes to chip level performance: modeling and design for conventional and exploratory concepts. In: 2020 IEEE international electron devices meeting (IEDM) pp. 32.6.1\u201332.6.4.","DOI":"10.1109\/IEDM13553.2020.9371945"},{"key":"e_1_3_5_251_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.50"},{"key":"e_1_3_5_252_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.2877839"},{"key":"e_1_3_5_253_1","doi-asserted-by":"crossref","unstructured":"Ikarashi Y Bernstein GL Reinking A et al. (2022) Exocompilation for productive programming of hardware accelerators. In: Proceedings of the 43rd ACM SIGPLAN international conference on programming language design and implementation PLDI 2022. New York NY: Association for Computing Machinery pp. 703\u2013718.","DOI":"10.1145\/3519939.3523446"},{"key":"e_1_3_5_254_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1977.1055718"},{"key":"e_1_3_5_255_1","doi-asserted-by":"crossref","unstructured":"Ingerly DB Amin S Aryasomayajula L et al. (2019) Foveros: 3D integration and the use of face-to-face chip stacking for logic devices. In: 2019 IEEE international electron devices meeting (IEDM) pp. 19.6.1\u201319.6.4.","DOI":"10.1109\/IEDM19573.2019.8993637"},{"key":"e_1_3_5_256_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2009.03.129"},{"key":"e_1_3_5_257_1","doi-asserted-by":"crossref","unstructured":"Iyer R (2012) Accelerator-rich architectures: implications opportunities and challenges. In: 17th Asia and South Pacific design automation conference pp. 106\u2013107.","DOI":"10.1109\/ASPDAC.2012.6164927"},{"key":"e_1_3_5_258_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2021.3114903"},{"key":"e_1_3_5_259_1","doi-asserted-by":"publisher","DOI":"10.1109\/95.705467"},{"key":"e_1_3_5_260_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-76387-9_1"},{"key":"e_1_3_5_261_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSAC.1984.1146031"},{"key":"e_1_3_5_262_1","unstructured":"Jia Z Tillman B Maggioni M et al. (2019) Dissecting the graphcore IPU architecture via microbenchmarking."},{"key":"e_1_3_5_263_1","doi-asserted-by":"crossref","unstructured":"Jiang H (2022) Intel\u2019s Ponte Vecchio GPU: architecture systems & software. In: 2022 IEEE hot chips 34 symposium (HCS). Los Alamitos CA: IEEE Computer Society pp. 1\u201329.","DOI":"10.1109\/HCS55958.2022.9895631"},{"key":"e_1_3_5_264_1","doi-asserted-by":"crossref","unstructured":"Jim\u00e9nez V Gioiosa R Cazorla FJ et al. (2012) Making data prefetch smarter: adaptive prefetching on POWER7. In: Proceedings of the 21st international conference on parallel architectures and compilation techniques PACT \u201912. New York NY: Association for Computing Machinery pp. 137\u2013146.","DOI":"10.1145\/2370816.2370837"},{"key":"e_1_3_5_265_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-47597-4_11"},{"key":"e_1_3_5_266_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2918851"},{"key":"e_1_3_5_267_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-10-0448-3_35"},{"key":"e_1_3_5_268_1","doi-asserted-by":"crossref","unstructured":"Jouppi NP Wall DW (1989) Available instruction-level parallelism for superscalar and superpipelined machines. In: Proceedings of the third international conference on architectural support for programming languages and operating systems ASPLOS III. New York NY: Association for Computing Machinery pp. 272\u2013282.","DOI":"10.1145\/70082.68207"},{"key":"e_1_3_5_269_1","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080246"},{"key":"e_1_3_5_270_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.032271057"},{"key":"e_1_3_5_271_1","doi-asserted-by":"publisher","DOI":"10.1145\/3360307"},{"key":"e_1_3_5_272_1","doi-asserted-by":"crossref","unstructured":"Jouppi NP Hyun Yoon D Ashcraft M et al. (2021) Ten lessons from three generations shaped Google\u2019s TPUv4i: industrial product. In: 2021 ACM\/IEEE 48th annual international symposium on computer architecture (ISCA). pp. 1\u201314.","DOI":"10.1109\/ISCA52012.2021.00010"},{"key":"e_1_3_5_273_1","doi-asserted-by":"crossref","unstructured":"Jouppi N Kurian G Li S et al. (2023) TPU v4: an optically reconfigurable supercomputer for machine learning with hardware support for embeddings. In: Proceedings of the 50th annual international symposium on computer architecture ISCA \u201923. New York NY: Association for Computing Machinery pp. 1\u201314.","DOI":"10.1145\/3579371.3589350"},{"key":"e_1_3_5_274_1","doi-asserted-by":"crossref","unstructured":"Juan T Navarro JJ Temam O (1997) Data caches for superscalar processors. In: Proceedings of the 11th international conference on supercomputing ICS \u201997. New York NY: Association for Computing Machinery pp. 60\u201367.","DOI":"10.1145\/263580.263595"},{"key":"e_1_3_5_275_1","doi-asserted-by":"crossref","unstructured":"Juan PS Alonso-Jord\u00e1 P Quintana-Ort\u00ed ES (2021) High performance and energy efficient integer matrix multiplication for deep learning. In: 2021 29th Euromicro international conference on parallel distributed and network-based processing (PDP). Institute of Electrical and Electronics Engineers pp. 122\u2013125.","DOI":"10.1109\/PDP52278.2021.00027"},{"key":"e_1_3_5_276_1","doi-asserted-by":"crossref","unstructured":"Kao J Narendra S Chandrakasan A (2002) Subthreshold leakage modeling and reduction techniques. In: Proceedings of the 2002 IEEE\/ACM international conference on computer-aided design ICCAD \u201902. New York NY: Association for Computing Machinery pp. 141\u2013148.","DOI":"10.1145\/774572.774593"},{"key":"e_1_3_5_277_1","doi-asserted-by":"crossref","unstructured":"Kaplan R (2024) Intel Gaudi 3 AI accelerator: architected for Gen AI training and inference. In: 2024 IEEE hot chips 36 symposium (HCS). IEEE pp. 1\u201316.","DOI":"10.1109\/HCS61935.2024.10665178"},{"key":"e_1_3_5_278_1","doi-asserted-by":"crossref","unstructured":"Kapur P Saraswat K (2002) Comparisons between electrical and optical interconnects for on-chip signaling. In: Proceedings of the IEEE 2002 international interconnect technology conference (Cat. No.02EX519) pp. 89\u201391.","DOI":"10.1109\/IITC.2002.1014897"},{"key":"e_1_3_5_279_1","doi-asserted-by":"publisher","DOI":"10.1109\/16.992868"},{"key":"e_1_3_5_280_1","doi-asserted-by":"crossref","unstructured":"Kara K Hagleitner C Diamantopoulos D et al. (2020) High bandwidth memory on FPGAs: a data analytics perspective. In: 2020 30th international conference on field-programmable logic and applications (FPL) pp. 1\u20138.","DOI":"10.1109\/FPL50879.2020.00013"},{"key":"e_1_3_5_281_1","doi-asserted-by":"publisher","DOI":"10.1515\/nanoph-2020-0204"},{"key":"e_1_3_5_282_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2004.14"},{"key":"e_1_3_5_283_1","doi-asserted-by":"crossref","unstructured":"Karstensen H Auracher F Ebel N et al. (2000) Module packaging for high-speed serial and parallel transmission. In: 2000 Proceedings. 50th Electronic components and technology conference (Cat. No.00CH37070) pp. 479\u2013486.","DOI":"10.1109\/ECTC.2000.853200"},{"key":"e_1_3_5_284_1","doi-asserted-by":"crossref","unstructured":"K\u00e4sgen PS Weinhardt M Hochberger C (2018) A coarse-grained reconfigurable array for high-performance computing applications. In: 2018 International conference on reconfigurable computing and FPGAs (ReConFig) pp. 1\u20134.","DOI":"10.1109\/RECONFIG.2018.8641720"},{"key":"e_1_3_5_285_1","doi-asserted-by":"publisher","DOI":"10.1117\/12.372647"},{"key":"e_1_3_5_286_1","doi-asserted-by":"publisher","DOI":"10.1108\/13565360710745601"},{"key":"e_1_3_5_287_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2014.2360787"},{"key":"e_1_3_5_288_1","doi-asserted-by":"crossref","unstructured":"Kaushik P Rao AM Singh DP et al. (2021) Cloud computing and comparison based on service and performance between Amazon AWS Microsoft Azure and Google Cloud. In: 2021 International conference on technological advancements and innovations (ICTAI) pp. 268\u2013273.","DOI":"10.1109\/ICTAI53825.2021.9673425"},{"key":"e_1_3_5_289_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-01721-6_4"},{"key":"e_1_3_5_290_1","doi-asserted-by":"crossref","unstructured":"Keckler SW Dally WJ Maskit D et al. (1998) Exploiting fine-grain thread level parallelism on the MIT Multi-ALU processor. In: Proceedings of the 25th annual international symposium on computer architecture ISCA \u201998. USA: IEEE Computer Society pp. 306\u2013317.","DOI":"10.1109\/ISCA.1998.694790"},{"key":"e_1_3_5_291_1","doi-asserted-by":"crossref","unstructured":"Kelleher A (2022) Celebrating 75 years of the transistor A look at the evolution of Moore\u2019s law innovation. In: 2022 International electron devices meeting (IEDM) pp. 1.1.1\u20131.1.5.","DOI":"10.1109\/IEDM45625.2022.10019538"},{"key":"e_1_3_5_292_1","doi-asserted-by":"crossref","unstructured":"Keutzer K Malik S Newton A (2002) From ASIC to ASIP: the next design discontinuity. In: Proceedings. IEEE international conference on computer design: VLSI in computers and processors pp. 84\u201390.","DOI":"10.1109\/ICCD.2002.1106752"},{"key":"e_1_3_5_293_1","doi-asserted-by":"crossref","unstructured":"Khaldi D Luo Y Yu B et al. (2021) Extending LLVM IR for DPC++ matrix support: a case study with Intel\u00ae advanced matrix extensions (Intel\u00ae AMX). In: 2021 IEEE\/ACM 7th workshop on the LLVM compiler infrastructure in HPC (LLVM-HPC) pp. 20\u201326.","DOI":"10.1109\/LLVMHPC54804.2021.00008"},{"key":"e_1_3_5_294_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAPT.2009.2037608"},{"key":"e_1_3_5_295_1","doi-asserted-by":"crossref","unstructured":"Khazraee M Zhang L Vega L et al. (2017) Moonwalk: NRE optimization in ASIC clouds. In: Proceedings of the twenty-second international conference on architectural support for programming languages and operating systems ASPLOS \u201917. New York NY: Association for Computing Machinery pp. 511\u2013526.","DOI":"10.1145\/3037697.3037749"},{"key":"e_1_3_5_296_1","unstructured":"Killian Z (2023) AMD\u2019s Zen 4 I\/O die shot reveals a fascinating Ryzen CCD detail."},{"issue":"12","key":"e_1_3_5_297_1","first-page":"68","article-title":"Leakage current: Moore\u2019s law meets static power","volume":"36","author":"Kim N","year":"2003","unstructured":"Kim N, Austin T, Baauw D, et al. (2003) Leakage current: Moore\u2019s law meets static power. Computer 36(12): 68\u201375.","journal-title":"Computer"},{"key":"e_1_3_5_298_1","doi-asserted-by":"crossref","unstructured":"Kim S Lee J Yang J et al. (2005) Novel instructions and their hardware architecture for video signal processing. In: 2005 IEEE international symposium on circuits and systems (ISCAS) Vol. 4 pp. 3323\u20133326.","DOI":"10.1109\/ISCAS.2005.1465339"},{"key":"e_1_3_5_299_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-02381-6_2"},{"key":"e_1_3_5_300_1","unstructured":"Kim S Gholami A Yao Z et al. (2021) I-BERT: integer-only BERT quantization. In: Meila M Zhang T (eds) Proceedings of the 38th international conference on machine learning proceedings of machine learning research. PMLR Vol. 139 pp. 5506\u20135518."},{"key":"e_1_3_5_301_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0375-9601(02)01365-8"},{"key":"e_1_3_5_302_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.1004576"},{"key":"e_1_3_5_303_1","doi-asserted-by":"crossref","unstructured":"Knowles S (2021) Graphcore. In: 2021 IEEE hot chips 33 symposium (HCS) pp. 1\u201325.","DOI":"10.1109\/HCS52781.2021.9567075"},{"key":"e_1_3_5_304_1","doi-asserted-by":"crossref","unstructured":"Ko H (2022) High-speed serial link trend and technical challenge. In: 2022 IEEE Asian solid-state circuits conference (A-SSCC) pp. 1\u20133.","DOI":"10.1109\/A-SSCC56115.2022.9980758"},{"key":"e_1_3_5_305_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.cag.2004.08.009"},{"issue":"2","key":"e_1_3_5_306_1","first-page":"129","article-title":"On-chip optical interconnects","volume":"8","author":"Kobrinsky MJ","year":"2004","unstructured":"Kobrinsky MJ, Block BA, Jun-Fei Z, et al. (2004) On-chip optical interconnects. Intel Technology Journal 8(2): 129\u2013141.","journal-title":"Intel Technology Journal"},{"key":"e_1_3_5_307_1","doi-asserted-by":"crossref","unstructured":"Kocanda P Kos A (2015) Static and dynamic energy losses vs. temperature in different CMOS technologies. In: 2015 22nd international conference mixed design of integrated circuits & systems (MIXDES) pp. 446\u2013449.","DOI":"10.1109\/MIXDES.2015.7208560"},{"key":"e_1_3_5_308_1","doi-asserted-by":"publisher","DOI":"10.1145\/3296979.3192379"},{"key":"e_1_3_5_309_1","doi-asserted-by":"crossref","unstructured":"Kohli P Sobczak M Bowin J et al. (2001) Advanced thermal interface materials for enhanced flip chip BGA. In: 2001 Proceedings. 51st Electronic components and technology conference (Cat. No.01CH37220) pp. 564\u2013570.","DOI":"10.1109\/ECTC.2001.927784"},{"key":"e_1_3_5_310_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCHMT.1981.1135787"},{"key":"e_1_3_5_311_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.909045"},{"key":"e_1_3_5_312_1","doi-asserted-by":"publisher","DOI":"10.1145\/3534933"},{"key":"e_1_3_5_313_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.710867"},{"key":"e_1_3_5_314_1","doi-asserted-by":"publisher","DOI":"10.1145\/3563946"},{"key":"e_1_3_5_315_1","first-page":"39","volume-title":"Instruction Scheduling in Microprocessors","author":"K\u00fc\u00e7\u00fck G","year":"2013","unstructured":"K\u00fc\u00e7\u00fck G, G\u00fcney \u0130, Ponomarev D (2013) Instruction Scheduling in Microprocessors. Chapter 2. Springer Berlin Heidelberg, pp. 39\u201360."},{"key":"e_1_3_5_316_1","doi-asserted-by":"crossref","unstructured":"Kudo H Takano T Akazawa M et al. (2021) High-speed high-density and highly-manufacturable Cu-filled through-glass-via channel (Cu bridge) for multi-chiplet systems. In: 2021 IEEE 71st electronic components and technology conference (ECTC) pp. 1031\u20131037.","DOI":"10.1109\/ECTC32696.2021.00169"},{"key":"e_1_3_5_317_1","doi-asserted-by":"crossref","unstructured":"Kumar K Ramkumar K Kaur A et al. (2020) A survey on hardware implementation of cryptographic algorithms using field programmable gate array. In: 2020 IEEE 9th international conference on communication systems and network technologies (CSNT) pp. 189\u2013194.","DOI":"10.1109\/CSNT48778.2020.9115742"},{"key":"e_1_3_5_318_1","doi-asserted-by":"crossref","unstructured":"Kuon I Rose J (2006) Measuring the gap between FPGAs and ASICs. In: Proceedings of the 2006 ACM\/SIGDA 14th international symposium on field programmable gate arrays FPGA \u201906. New York NY: Association for Computing Machinery pp. 21\u201330.","DOI":"10.1145\/1117201.1117205"},{"key":"e_1_3_5_319_1","doi-asserted-by":"crossref","unstructured":"Lachance R Lavoie H Montanari A (1997) Corrosion\/migration study of flip chip underfill and ceramic overcoating. In: 1997 Proceedings 47th electronic components and technology conference pp. 885\u2013889.","DOI":"10.1109\/ECTC.1997.606274"},{"key":"e_1_3_5_320_1","doi-asserted-by":"crossref","unstructured":"Lai JW (2021) Opportunity and challenge of Chiplet-based HPC and AIoT. In: 2021 international symposium on VLSI design automation and test (VLSI-DAT) pp. 1\u20132.","DOI":"10.1109\/VLSI-DAT52063.2021.9427309"},{"key":"e_1_3_5_321_1","doi-asserted-by":"crossref","unstructured":"Langhammer M Pasca B (2015) Floating-point DSP block architecture for FPGAs. In: Proceedings of the 2015 ACM\/SIGDA international symposium on field-programmable gate arrays FPGA \u201915. New York NY: Association for Computing Machinery pp. 117\u2013125.","DOI":"10.1145\/2684746.2689071"},{"key":"e_1_3_5_322_1","doi-asserted-by":"crossref","unstructured":"Langhammer M Nurvitadhi E Pasca B et al. (2021) Stratix 10 NX architecture and applications. In: The 2021 ACM\/SIGDA international symposium on field-programmable gate arrays FPGA \u201921. New York NY: Association for Computing Machinery pp. 57\u201367.","DOI":"10.1145\/3431920.3439293"},{"key":"e_1_3_5_323_1","volume-title":"Modern Digital and Analog Communication","author":"Lathi BP","year":"2022","unstructured":"Lathi BP, Ding Z (2022) Modern Digital and Analog Communication. The Oxford Series in Electrical and Computer Engineering. 5 edition. Oxford University Press.","edition":"5"},{"key":"e_1_3_5_324_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2021.3112025"},{"key":"e_1_3_5_325_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2013.6576344"},{"key":"e_1_3_5_326_1","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.3336"},{"key":"e_1_3_5_327_1","unstructured":"Le Sueur E Heiser G (2010) Dynamic voltage and frequency scaling: the laws of diminishing returns. In: Proceedings of the 2010 international conference on power aware computing and systems HotPower\u201910. USA: USENIX Association pp. 1\u20138."},{"key":"e_1_3_5_328_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.60522"},{"key":"e_1_3_5_329_1","doi-asserted-by":"crossref","unstructured":"Lee SY Wu CJ (2014) Characterizing the latency hiding ability of GPUs. In: 2014 IEEE international symposium on performance analysis of systems and software (ISPASS) pp. 145\u2013146.","DOI":"10.1109\/ISPASS.2014.6844477"},{"key":"e_1_3_5_330_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2227853"},{"key":"e_1_3_5_331_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3152217"},{"key":"e_1_3_5_332_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.aam9744"},{"key":"e_1_3_5_333_1","doi-asserted-by":"crossref","unstructured":"Lenihan TG Matthew L Vardaman EJ (2013) Developments in 2.5D: the role of silicon interposers. In: 2013 IEEE 15th electronics packaging technology conference (EPTC 2013) pp. 53\u201355.","DOI":"10.1109\/EPTC.2013.6745683"},{"key":"e_1_3_5_334_1","doi-asserted-by":"crossref","unstructured":"Leong PHW (2008) Recent trends in FPGA architectures and applications. In: 4th IEEE international symposium on electronic design test and applications (Delta 2008) pp. 137\u2013141.","DOI":"10.1109\/DELTA.2008.14"},{"issue":"7","key":"e_1_3_5_335_1","first-page":"1878","article-title":"Accelerating binarized neural networks via bit-tensor-cores in turing GPUs","volume":"32","author":"Li A","year":"2021","unstructured":"Li A, Su S (2021) Accelerating binarized neural networks via bit-tensor-cores in turing GPUs. IEEE Transactions on Parallel and Distributed Systems 32(7): 1878\u20131891.","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"key":"e_1_3_5_336_1","doi-asserted-by":"crossref","unstructured":"Li Y Li D Cui W et al. (2011) Research based on OSI model. In: 2011 IEEE 3rd international conference on communication software and networks pp. 554\u2013557.","DOI":"10.1109\/ICCSN.2011.6014631"},{"key":"e_1_3_5_337_1","doi-asserted-by":"crossref","unstructured":"Li S Reddy D Jacob B (2018) A performance & power comparison of modern high-speed DRAM architectures. In: Proceedings of the international symposium on memory systems MEMSYS \u201918. New York NY: Association for Computing Machinery pp. 341\u2013353.","DOI":"10.1145\/3240302.3240315"},{"key":"e_1_3_5_338_1","doi-asserted-by":"publisher","DOI":"10.1002\/anie.201902516"},{"key":"e_1_3_5_339_1","doi-asserted-by":"publisher","DOI":"10.3390\/electronics9040670"},{"key":"e_1_3_5_340_1","doi-asserted-by":"crossref","unstructured":"Li G Xue J Liu L et al. (2021) Unleashing the low-precision computation potential of tensor cores on GPUs. In: 2021 IEEE\/ACM international symposium on code generation and optimization (CGO) pp. 90\u2013102.","DOI":"10.1109\/CGO51591.2021.9370335"},{"key":"e_1_3_5_341_1","doi-asserted-by":"publisher","DOI":"10.1002\/adom.202201008"},{"key":"e_1_3_5_342_1","doi-asserted-by":"crossref","unstructured":"Lidow A Sheridan G (2003) Defining the future for microprocessor power delivery. In: Eighteenth annual IEEE applied power electronics conference and exposition 2003. APEC \u201903 Vol. 1. pp. 3\u20139.","DOI":"10.1109\/APEC.2003.1179168"},{"key":"e_1_3_5_343_1","doi-asserted-by":"crossref","unstructured":"Lie S (2022) Cerebras architecture deep dive: first look inside the HW\/SW co-design for deep learning: cerebras systems. In: 2022 IEEE hot chips 34 symposium (HCS) pp. 1\u201334.","DOI":"10.1109\/HCS55958.2022.9895479"},{"key":"e_1_3_5_344_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2024.3386628"},{"key":"e_1_3_5_345_1","doi-asserted-by":"publisher","DOI":"10.1145\/3177964"},{"key":"e_1_3_5_346_1","doi-asserted-by":"crossref","unstructured":"Lin Y Liang R Li Y et al. (2022) Mapping large scale finite element computing on to wafer-scale engines. In: 2022 27th Asia and South Pacific design automation conference (ASP-DAC) pp. 147\u2013153.","DOI":"10.1109\/ASP-DAC52403.2022.9712538"},{"key":"e_1_3_5_347_1","doi-asserted-by":"crossref","unstructured":"Lindholm E Kilgard MJ Moreton H (2001) A user-programmable vertex engine. In: Proceedings of the 28th annual conference on computer graphics and interactive techniques SIGGRAPH \u201901. New York NY: Association for Computing Machinery pp. 149\u2013158.","DOI":"10.1145\/383259.383274"},{"key":"e_1_3_5_348_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.31"},{"key":"e_1_3_5_349_1","doi-asserted-by":"crossref","unstructured":"Liu X Liu Y (2017) Multi-functional serial communication interface design based on FPGA. In: 2017 3rd IEEE international conference on computer and communications (ICCC) pp. 758\u2013761.","DOI":"10.1109\/CompComm.2017.8322645"},{"key":"e_1_3_5_350_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.179198"},{"key":"e_1_3_5_351_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.293111"},{"key":"e_1_3_5_352_1","doi-asserted-by":"publisher","DOI":"10.1145\/3357375"},{"key":"e_1_3_5_353_1","doi-asserted-by":"publisher","DOI":"10.1002\/9781118256053.ch34"},{"key":"e_1_3_5_354_1","volume-title":"The Communications Handbook","author":"LoCicero JL","year":"2018","unstructured":"LoCicero JL, Patel BP (2018) The Communications Handbook. CRC Press."},{"key":"e_1_3_5_355_1","unstructured":"Locuza (2020) Zen 2 (+1) layman die shot analysis (tutorial style) - Part 6."},{"key":"e_1_3_5_356_1","unstructured":"Locuza (2022) Zen evolution: a small overview."},{"key":"e_1_3_5_357_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCC.2024.3393895"},{"key":"e_1_3_5_358_1","doi-asserted-by":"crossref","unstructured":"Loh GH Naffziger S Lepak K (2021) Understanding chiplets today to anticipate future integration opportunities and limits. In: 2021 design automation and test in Europe conference & exhibition (DATE) pp. 142\u2013145.","DOI":"10.23919\/DATE51398.2021.9474021"},{"key":"e_1_3_5_359_1","unstructured":"Loh GH Schulte MJ Ignatowski M et al. (2023) A research retrospective on AMD\u2019s exascale computing journey. In: Proceedings of the 50th annual international symposium on computer architecture ISCA \u201923. New York NY: Association for Computing Machinery pp. 1\u201314."},{"key":"e_1_3_5_360_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2007.59"},{"key":"e_1_3_5_361_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00170-006-0800-3"},{"issue":"99","key":"e_1_3_5_362_1","first-page":"1","article-title":"MS-CLS: an effective partitioning and placement metaheuristic for wafer-scale physics modeling","author":"Luo C","year":"2023","unstructured":"Luo C, Su Z, L\u00fc Z (2023) MS-CLS: an effective partitioning and placement metaheuristic for wafer-scale physics modeling. IEEE Transactions on Emerging Topics in Computational Intelligence PP(99): 1\u201315.","journal-title":"IEEE Transactions on Emerging Topics in Computational Intelligence"},{"key":"e_1_3_5_363_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2015.7065415"},{"key":"e_1_3_5_364_1","doi-asserted-by":"crossref","unstructured":"Macri J (2015) AMD\u2019s next generation GPU and high bandwidth memory architecture: FURY. In: 2015 IEEE hot chips 27 symposium (HCS) pp. 1\u201326.","DOI":"10.1109\/HOTCHIPS.2015.7477461"},{"key":"e_1_3_5_365_1","doi-asserted-by":"publisher","DOI":"10.1007\/s41781-021-00057-z"},{"key":"e_1_3_5_366_1","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511807046"},{"key":"e_1_3_5_367_1","doi-asserted-by":"crossref","unstructured":"Magaki I Khazraee M Gutierrez LV et al. (2016) ASIC clouds: specializing the datacenter. In: 2016 ACM\/IEEE 43rd annual international symposium on computer architecture (ISCA) pp. 178\u2013190.","DOI":"10.1109\/ISCA.2016.25"},{"issue":"1","key":"e_1_3_5_368_1","first-page":"1","article-title":"Hyper-threading technology: impact on compute-intensive workloads","volume":"6","author":"Magro W","year":"2002","unstructured":"Magro W, Petersen P, Shah S (2002) Hyper-threading technology: impact on compute-intensive workloads. Intel Technology Journal 6(1): 1.","journal-title":"Intel Technology Journal"},{"key":"e_1_3_5_369_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.879800"},{"key":"e_1_3_5_370_1","doi-asserted-by":"crossref","unstructured":"Mahajan R Mallik D Sankman R et al. (2006b) Advances and challenges in flip-chip packaging. In: IEEE custom integrated circuits conference 2006 pp. 703\u2013709.","DOI":"10.1109\/CICC.2006.320896"},{"key":"e_1_3_5_371_1","doi-asserted-by":"crossref","unstructured":"Mallik A Ryckaert J Kim RH et al. (2019) Economics of semiconductor scaling - a cost analysis for advanced technology node. In: 2019 symposium on VLSI technology pp. T202\u2013T203.","DOI":"10.23919\/VLSIT.2019.8776521"},{"key":"e_1_3_5_372_1","doi-asserted-by":"crossref","unstructured":"Mandal A Fowler R Porterfield A (2010) Modeling memory concurrency for multi-socket multi-core systems. In: 2010 IEEE international symposium on performance analysis of systems & software (ISPASS) pp. 66\u201375.","DOI":"10.1109\/ISPASS.2010.5452064"},{"key":"e_1_3_5_373_1","doi-asserted-by":"crossref","unstructured":"Marculescu D Talpes E (2005) Variability and energy awareness: a microarchitecture-level perspective. In: Proceedings of the 42nd annual design automation conference DAC \u201905. New York NY: Association for Computing Machinery pp. 11\u201316.","DOI":"10.1145\/1065579.1065588"},{"key":"e_1_3_5_374_1","doi-asserted-by":"crossref","unstructured":"Markidis S Chien SWD Laure E et al. (2018) NVIDIA tensor core programmability performance & precision. In: 2018 IEEE international parallel and distributed processing symposium workshops (IPDPSW) pp. 522\u2013531.","DOI":"10.1109\/IPDPSW.2018.00091"},{"key":"e_1_3_5_375_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.precisioneng.2021.10.001"},{"key":"e_1_3_5_376_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2011.133"},{"key":"e_1_3_5_377_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.820764"},{"key":"e_1_3_5_378_1","doi-asserted-by":"crossref","unstructured":"Martens B Walterbusch M Teuteberg F (2012) Costing of cloud computing services: a total cost of ownership approach. In: 2012 45th Hawaii international conference on system sciences pp. 1563\u20131572.","DOI":"10.1109\/HICSS.2012.186"},{"key":"e_1_3_5_379_1","doi-asserted-by":"crossref","unstructured":"Martin KJM (2022) Twenty years of automated methods for mapping applications on CGRA. In: 2022 IEEE international parallel and distributed processing symposium workshops (IPDPSW) pp. 679\u2013686.","DOI":"10.1109\/IPDPSW55747.2022.00118"},{"key":"e_1_3_5_380_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-70129-5_4"},{"key":"e_1_3_5_381_1","doi-asserted-by":"crossref","unstructured":"Matteis TD Licht JF Hoefler T (2020) FBLAS: streaming linear algebra on FPGA. In: SC20: International conference for high performance computing networking storage and analysis pp. 1\u201313.","DOI":"10.1109\/SC41405.2020.00063"},{"key":"e_1_3_5_382_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2021.3086541"},{"key":"e_1_3_5_383_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1983.12780"},{"key":"e_1_3_5_384_1","doi-asserted-by":"crossref","unstructured":"Mechaik M (2001) An evaluation of single-ended and differential impedance in PCBs. In: Proceedings of the IEEE 2001. 2nd international symposium on quality electronic design pp. 301\u2013306.","DOI":"10.1109\/ISQED.2001.915247"},{"key":"e_1_3_5_385_1","doi-asserted-by":"crossref","unstructured":"Mehis A Radhakrishnan R (2002) Optimizing applications for performance on the pentium 4 architecture. In: 2002 IEEE international workshop on workload characterization pp. 59\u201367.","DOI":"10.1109\/WWC.2002.1226494"},{"key":"e_1_3_5_386_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-007-0152-8"},{"key":"e_1_3_5_387_1","doi-asserted-by":"crossref","unstructured":"Meijer M Pessolano F de Gyvez JP (2004) Technology exploration for adaptive power and frequency scaling in 90nm CMOS. In: Proceedings of the 2004 international symposium on low power electronics and design ISLPED \u201904. New York NY: Association for Computing Machinery pp. 14\u201319.","DOI":"10.1145\/1013235.1013245"},{"key":"e_1_3_5_388_1","doi-asserted-by":"publisher","DOI":"10.3390\/nano12030485"},{"key":"e_1_3_5_389_1","doi-asserted-by":"publisher","DOI":"10.1145\/3411757.3411759"},{"key":"e_1_3_5_390_1","doi-asserted-by":"publisher","DOI":"10.1109\/SURV.2010.020110.00079"},{"key":"e_1_3_5_391_1","doi-asserted-by":"publisher","DOI":"10.1109\/49.62819"},{"key":"e_1_3_5_392_1","doi-asserted-by":"crossref","unstructured":"Mhaboobkhan F Fathimaparveen M Gokila K et al. (2019) Implementation of high speed data transfer serialized 128\/130 bit encoding algorithm using 90nm technology. In: 2019 5th International conference on advanced computing & communication systems (ICACCS) pp. 732\u2013736.","DOI":"10.1109\/ICACCS.2019.8728312"},{"key":"e_1_3_5_393_1","first-page":"1","volume-title":"International Conference on Learning Representations","author":"Micikevicius P","year":"2018","unstructured":"Micikevicius P, Narang S, Alben J, et al. (2018) Mixed precision training. In: International Conference on Learning Representations. Open Review, pp. 1\u201312."},{"key":"e_1_3_5_394_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2014298"},{"key":"e_1_3_5_395_1","doi-asserted-by":"publisher","DOI":"10.1006\/jpdc.1996.1285"},{"key":"e_1_3_5_396_1","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.4666"},{"key":"e_1_3_5_397_1","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.5742"},{"key":"e_1_3_5_398_1","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.5742"},{"key":"e_1_3_5_399_1","doi-asserted-by":"crossref","unstructured":"Miyake T Yamashita T Asari N et al. (2001) Design methodology of high performance microprocessor using ultra-low threshold voltage CMOS. In: Proceedings of the IEEE 2001 custom integrated circuits conference (Cat. No.01CH37169) pp. 275\u2013278.","DOI":"10.1109\/CICC.2001.929773"},{"key":"e_1_3_5_400_1","first-page":"1","article-title":"Power analysis of mobile 3D graphics","volume":"1","author":"Mochocki B","year":"2006","unstructured":"Mochocki B, Lahiri K, Cadambi S (2006) Power analysis of mobile 3D graphics. Proceedings of the Design Automation & Test in Europe Conference 1: 1\u20136.","journal-title":"Proceedings of the Design Automation & Test in Europe Conference"},{"key":"e_1_3_5_401_1","doi-asserted-by":"crossref","unstructured":"Modi H Spracklen L Chou Y et al. (2005) Accurate modeling of aggressive speculation in modern microprocessor architectures. In: 13th IEEE international symposium on modeling analysis and simulation of computer and telecommunication systems pp. 75\u201384.","DOI":"10.1109\/MASCOTS.2005.12"},{"key":"e_1_3_5_402_1","doi-asserted-by":"crossref","unstructured":"Mohapatra S Gupta HS Singh J et al. (2017) A 64b\/66b line encoding for high speed serializers. In: 2017 30th International conference on VLSI design and 2017 16th international conference on embedded systems (VLSID) pp. 303\u2013308.","DOI":"10.1109\/VLSID.2017.47"},{"issue":"8","key":"e_1_3_5_403_1","first-page":"114","article-title":"Cramming more components onto integrated circuits","volume":"38","author":"Moore GE","year":"1965","unstructured":"Moore GE (1965) Cramming more components onto integrated circuits. Electronics 38(8): 114\u2013117.","journal-title":"Electronics"},{"key":"e_1_3_5_404_1","doi-asserted-by":"crossref","unstructured":"Moore GE (2006) Progress in digital integrated electronics [Technical literaiture Copyright 1975 IEEE. Reprinted with permission. Technical Digest. International Electron Devices Meeting IEEE 1975 pp. 11-13]. IEEE Solid-State Circuits Society Newsletter 11(3): 36\u201337 originally published in 1975.","DOI":"10.1109\/N-SSC.2006.4804410"},{"key":"e_1_3_5_405_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2020.9150552"},{"key":"e_1_3_5_406_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2022.9976480"},{"key":"e_1_3_5_407_1","unstructured":"Mujtaba H (2015) Intel\u2019s 10nm Knights Hill powered Aurora supercomputer to feature up to 180 PetaFlops computational power \u2013 2018 launch scheduled."},{"key":"e_1_3_5_408_1","unstructured":"Mujtaba H (2022) AMD SP5 socket pictured in all its glory LGA 6096 for future EPYC CPUs with 96 cores & above."},{"key":"e_1_3_5_409_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEMC.2015.2427362"},{"key":"e_1_3_5_410_1","doi-asserted-by":"crossref","unstructured":"Munger B Wilcox K Sniderman J et al. (2023) \u201cZen 4\u201d: the AMD 5nm 5.7GHz x86-64 microprocessor core. In: 2023 IEEE international solid- state circuits conference (ISSCC) pp. 38\u201339.","DOI":"10.1109\/ISSCC42615.2023.10067540"},{"key":"e_1_3_5_411_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.400426"},{"key":"e_1_3_5_412_1","doi-asserted-by":"crossref","unstructured":"Na N Wang J Long S et al. (2017) Exploring DDR4 address bus design for high speed memory interface. In: 2017 IEEE 67th Electronic components and technology conference (ECTC) pp. 1843\u20131848.","DOI":"10.1109\/ECTC.2017.247"},{"key":"e_1_3_5_413_1","doi-asserted-by":"crossref","unstructured":"Naeemi A Sarvari R Meindl J (2006) On-chip interconnect networks at the end of the roadmap: limits and nanotechnology opportunities. In: 2006 International interconnect technology conference pp. 201\u2013203.","DOI":"10.1109\/IITC.2006.1648693"},{"key":"e_1_3_5_414_1","doi-asserted-by":"crossref","unstructured":"Naffziger S Lepak K Paraschou M et al. (2020) 2.2 AMD chiplet architecture for high-performance server and desktop products. In: 2020 IEEE international solid- state circuits conference - (ISSCC) pp. 44\u201345.","DOI":"10.1109\/ISSCC19947.2020.9063103"},{"key":"e_1_3_5_415_1","doi-asserted-by":"crossref","unstructured":"Naffziger S Beck N Burd T et al. (2021) Pioneering chiplet technology and design for the AMD EPYCTM and RyzenTM processor families: industrial product. In: 2021 ACM\/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). pp. 57\u201370.","DOI":"10.1109\/ISCA52012.2021.00014"},{"key":"e_1_3_5_416_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2513673"},{"key":"e_1_3_5_417_1","doi-asserted-by":"crossref","unstructured":"Narayanan S Swamy BN Seznec A (2015) An empirical high level performance model for future many-cores. In: Proceedings of the 12th ACM international conference on computing Frontiers CF \u201915. New York NY: Association for Computing Machinery pp. 1\u20138.","DOI":"10.1145\/2742854.2742867"},{"key":"e_1_3_5_418_1","doi-asserted-by":"crossref","unstructured":"Nassif N Munch AO Molnar CL et al. (2022) Sapphire rapids: the next-generation Intel Xeon scalable processor. In: 2022 IEEE international solid- state circuits conference (ISSCC) Vol. 65 pp. 44\u201346.","DOI":"10.1109\/ISSCC42614.2022.9731107"},{"key":"e_1_3_5_419_1","doi-asserted-by":"publisher","DOI":"10.1006\/spmi.1999.0807"},{"key":"e_1_3_5_420_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.926733"},{"key":"e_1_3_5_421_1","doi-asserted-by":"crossref","unstructured":"Niu KP Anderson JH (2018) Compact area and performance modelling for CGRA architecture evaluation. In: 2018 International conference on field-programmable technology (FPT) pp. 126\u2013133.","DOI":"10.1109\/FPT.2018.00028"},{"key":"e_1_3_5_422_1","doi-asserted-by":"crossref","unstructured":"Nowatzki T Gangadhar V Ardalani N et al. (2017) Stream-dataflow acceleration. In: 2017 ACM\/IEEE 44th annual international symposium on computer architecture (ISCA) pp. 416\u2013429.","DOI":"10.1145\/3079856.3080255"},{"key":"e_1_3_5_423_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.755466"},{"key":"e_1_3_5_424_1","article-title":"Trends in research and development of lithography technology for next-generation LSIs","author":"Ogasawara A","year":"2002","unstructured":"Ogasawara A (2002) Trends in research and development of lithography technology for next-generation LSIs. Science & Technology Trends Quarterly Review.","journal-title":"Science & Technology Trends Quarterly Review"},{"key":"e_1_3_5_425_1","doi-asserted-by":"publisher","DOI":"10.1145\/1095408.1095418"},{"key":"e_1_3_5_426_1","doi-asserted-by":"publisher","DOI":"10.1111\/j.1467-8659.2007.01012.x"},{"key":"e_1_3_5_427_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCC.2017.2702586"},{"key":"e_1_3_5_428_1","doi-asserted-by":"crossref","unstructured":"Pai V Ranganathan P Adve S (1997) The impact of instruction-level parallelism on multiprocessor performance and simulation methodology. In: Proceedings third international symposium on high-performance computer architecture pp. 72\u201383.","DOI":"10.1109\/HPCA.1997.569611"},{"key":"e_1_3_5_429_1","doi-asserted-by":"publisher","DOI":"10.1145\/384286.264201"},{"key":"e_1_3_5_430_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2022.3178420"},{"key":"e_1_3_5_431_1","doi-asserted-by":"crossref","unstructured":"Pandey V Subramanian S Rangaraj S et al. (2005) Mechanical design and analysis of land grid array (LGA) sockets. In: International electronic packaging technical conference and exhibition advances in electronic packaging Parts A B and C pp. 1005\u20131011.","DOI":"10.1115\/IPACK2005-73360"},{"key":"e_1_3_5_432_1","doi-asserted-by":"crossref","unstructured":"Pandey AK Jangale A Narayan S (2020) Signal integrity and compliance test of DSI and CSI2 serial interface over MIPI D-PHY. In: 2020 IEEE 24th workshop on signal and power integrity (SPI) pp. 1\u20134.","DOI":"10.1109\/SPI48784.2020.9218161"},{"key":"e_1_3_5_433_1","doi-asserted-by":"crossref","unstructured":"Papadimitriou G Chatzidimitriou A Gizopoulos D (2019) Adaptive voltage\/frequency scaling and core allocation for balanced energy and performance on multicore CPUs. In: 2019 IEEE international symposium on high performance computer architecture (HPCA) pp. 133\u2013146.","DOI":"10.1109\/HPCA.2019.00033"},{"key":"e_1_3_5_434_1","doi-asserted-by":"crossref","unstructured":"Park H Park Y Mahlke S (2009) Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications. In: 2009 42nd annual IEEE\/ACM international symposium on microarchitecture (MICRO) pp. 370\u2013380.","DOI":"10.1145\/1669112.1669160"},{"key":"e_1_3_5_435_1","doi-asserted-by":"crossref","unstructured":"Parkhurst J Darringer J Grundmann B (2006) From single core to multi-core: preparing for a new exponential. In: Proceedings of the 2006 IEEE\/ACM international conference on computer-aided design ICCAD \u201906. New York NY: Association for Computing Machinery pp. 67\u201372.","DOI":"10.1145\/1233501.1233516"},{"key":"e_1_3_5_436_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2024118"},{"key":"e_1_3_5_437_1","first-page":"8024","volume-title":"Advances in Neural Information Processing Systems 32","author":"Paszke A","year":"2019","unstructured":"Paszke A, Gross S, Massa F, et al. (2019) PyTorch: an imperative style, high-performance deep learning library. In: Advances in Neural Information Processing Systems 32. Curran Associates, Inc., pp. 8024\u20138035."},{"key":"e_1_3_5_438_1","doi-asserted-by":"crossref","unstructured":"Patton G (2009) Semiconductor technology-trends challenges and opportunities. In: 2009 13th international workshop on computational electronics pp. 1\u20134.","DOI":"10.1109\/IWCE.2009.5091147"},{"key":"e_1_3_5_439_1","doi-asserted-by":"crossref","unstructured":"Paulin P (2004) DATE panel chips of the future: soft crunchy or hard? In: Proceedings design automation and test in Europe conference and exhibition Vol. 2 pp. 844\u2013849.","DOI":"10.1109\/DATE.2004.1268990"},{"key":"e_1_3_5_440_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2022.102561"},{"key":"e_1_3_5_441_1","volume-title":"The History of the GPU - Eras and Environment","author":"Peddie J","year":"2023","unstructured":"Peddie J (2023a) The History of the GPU - Eras and Environment. Springer International Publishing."},{"key":"e_1_3_5_442_1","volume-title":"The History of the GPU - New Developments","author":"Peddie J","year":"2023","unstructured":"Peddie J (2023b) The History of the GPU - New Developments. Springer International Publishing."},{"key":"e_1_3_5_443_1","volume-title":"The History of the GPU - Steps to Invention","author":"Peddie J","year":"2023","unstructured":"Peddie J (2023c) The History of the GPU - Steps to Invention. Springer International Publishing."},{"key":"e_1_3_5_444_1","doi-asserted-by":"crossref","unstructured":"Peleg A Weister U (1991) Future trends in microprocessors: out-of-order execution speculative branching and their CISC performance potential. In: 17th Convention of electrical and electronics engineers in Israel pp. 263\u2013266.","DOI":"10.1109\/EEIS.1991.217647"},{"key":"e_1_3_5_445_1","doi-asserted-by":"publisher","DOI":"10.1145\/242857.242865"},{"key":"e_1_3_5_446_1","doi-asserted-by":"crossref","unstructured":"Pellerite P Suhl D (1988) Sockets: considerations as an alternative to direct surface mounting of components. In: Fourth IEEE\/CHMT European international electronic manufacturing technology symposium pp. 89\u201391.","DOI":"10.1109\/EEMTS.1988.75962"},{"key":"e_1_3_5_447_1","doi-asserted-by":"crossref","unstructured":"Peng Z Fattal D Fiorentino M et al. (2010) Fabrication variations in SOI microrings for DWDM networks. In: 7th IEEE international conference on group IV photonics pp. 120\u2013122.","DOI":"10.1109\/GROUP4.2010.5643406"},{"key":"e_1_3_5_448_1","doi-asserted-by":"crossref","unstructured":"Peng IB Gioiosa R Kestor G et al. (2017) Exploring the performance benefit of hybrid memory system on HPC environments. In: 2017 IEEE international parallel and distributed processing symposium workshops (IPDPSW) pp. 683\u2013692.","DOI":"10.1109\/IPDPSW.2017.115"},{"key":"e_1_3_5_449_1","doi-asserted-by":"crossref","unstructured":"Pohl C Sattler KU (2018) Joins in a heterogeneous memory hierarchy: exploiting high-bandwidth memory. In: Proceedings of the 14th international workshop on data management on new hardware DAMON \u201918. New York NY: Association for Computing Machinery pp. 1\u201310.","DOI":"10.1145\/3211922.3211929"},{"key":"e_1_3_5_450_1","doi-asserted-by":"crossref","unstructured":"Prabhakar R Jairath S (2021) SambaNova SN10 RDU: accelerating software 2.0 with dataflow. In: 2021 IEEE hot chips 33 symposium (HCS) pp. 1\u201337.","DOI":"10.1109\/HCS52781.2021.9567250"},{"key":"e_1_3_5_451_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-18338-7_14"},{"key":"e_1_3_5_452_1","doi-asserted-by":"crossref","unstructured":"Prabhakar R Jairath S Shin JL (2022) SambaNova SN10 RDU: a 7nm dataflow architecture to accelerate software 2.0. 2022 IEEE international solid- state circuits conference (ISSCC) Vol. 65 pp. 350\u2013352.","DOI":"10.1109\/ISSCC42614.2022.9731612"},{"key":"e_1_3_5_453_1","doi-asserted-by":"crossref","unstructured":"Pratheek B Jawalkar N Basu A (2022) Designing virtual memory system of MCM GPUs. In: 2022 55th IEEE\/ACM international symposium on microarchitecture (MICRO) pp. 404\u2013422.","DOI":"10.1109\/MICRO56248.2022.00036"},{"key":"e_1_3_5_454_1","doi-asserted-by":"crossref","unstructured":"Prince B (1999) A tribute to graphics DRAMs. In: Records of the 1999 IEEE international workshop on memory technology design and testing pp. 123\u2013130.","DOI":"10.1109\/MTDT.1999.782693"},{"key":"e_1_3_5_455_1","doi-asserted-by":"crossref","unstructured":"Qasaimeh M Denolf K Lo J et al. (2019) Comparing energy efficiency of CPU GPU and FPGA implementations for vision kernels. In: 2019 IEEE international conference on embedded software and systems (ICESS) pp. 1\u20138.","DOI":"10.1109\/ICESS.2019.8782524"},{"key":"e_1_3_5_456_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.331409"},{"key":"e_1_3_5_457_1","doi-asserted-by":"crossref","unstructured":"Quinones E Parcerisa JM Gonzailez A (2007) Improving branch prediction and predicated execution in out-of-order processors. In: 2007 IEEE 13th international symposium on high performance computer architecture pp. 75\u201384.","DOI":"10.1109\/HPCA.2007.346186"},{"key":"e_1_3_5_458_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2021.3065690"},{"key":"e_1_3_5_459_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2878686"},{"key":"e_1_3_5_460_1","doi-asserted-by":"publisher","DOI":"10.1364\/AO.47.002961"},{"key":"e_1_3_5_461_1","doi-asserted-by":"crossref","unstructured":"Rakheja S Kumar V (2012) Comparison of electrical optical and plasmonic on-chip interconnects based on delay and energy considerations. In: Thirteenth international symposium on quality electronic design (ISQED) pp. 732\u2013739.","DOI":"10.1109\/ISQED.2012.6187573"},{"key":"e_1_3_5_462_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.865866"},{"key":"e_1_3_5_463_1","doi-asserted-by":"publisher","DOI":"10.1145\/356725.356729"},{"key":"e_1_3_5_464_1","doi-asserted-by":"crossref","unstructured":"Rashdan M El-Sayed F Salman M (2020) Performance comparison between SerDes and time-based serial links. In: 2020 7th International conference on electrical and electronics engineering (ICEEE) pp. 37\u201341.","DOI":"10.1109\/ICEEE49618.2020.9102626"},{"key":"e_1_3_5_465_1","first-page":"883","volume-title":"Instruction-Level Parallelism","author":"Rau BR","year":"2003","unstructured":"Rau BR, Fisher JA (2003) Instruction-Level Parallelism. Chapter I. John Wiley and Sons Ltd, pp. 883\u2013887."},{"key":"e_1_3_5_466_1","doi-asserted-by":"crossref","unstructured":"Ray J Hoe JC (2003) High-level modeling and FPGA prototyping of microprocessors. In: Proceedings of the 2003 ACM\/SIGDA eleventh international symposium on field programmable gate arrays FPGA \u201903. New York NY: Association for Computing Machinery pp. 100\u2013107.","DOI":"10.1145\/611817.611833"},{"key":"e_1_3_5_467_1","doi-asserted-by":"publisher","DOI":"10.1109\/COMST.2023.3259224"},{"key":"e_1_3_5_468_1","doi-asserted-by":"publisher","DOI":"10.1117\/1.JMM.18.4.040902"},{"key":"e_1_3_5_469_1","doi-asserted-by":"publisher","DOI":"10.1109\/41.744370"},{"key":"e_1_3_5_470_1","doi-asserted-by":"crossref","unstructured":"Robe T Banwell T Hodge J et al. (1993) 4B\/5B block code to SONET OC-3 (155-Mbit\/s) interface for ATM local area networks. In: Conference on optical fiber communication\/international conference on integrated optics and optical fiber communication. Optica Publishing Group p. WJ3.","DOI":"10.1364\/OFC.1993.WJ3"},{"key":"e_1_3_5_471_1","doi-asserted-by":"crossref","unstructured":"Rodriguez JN Canosa MC Pereira EH (2011) Improving electrical power grid visualization using geometry shaders. In: 2011 Eighth international conference computer graphics imaging and visualization pp. 177\u2013182.","DOI":"10.1109\/CGIV.2011.10"},{"key":"e_1_3_5_472_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4684-6419-1_18"},{"key":"e_1_3_5_473_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2474363"},{"key":"e_1_3_5_474_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.915377"},{"key":"e_1_3_5_475_1","doi-asserted-by":"publisher","DOI":"10.1145\/3503465"},{"key":"e_1_3_5_476_1","doi-asserted-by":"crossref","unstructured":"Rose J (2004) Hard vs. soft: the central question of pre-fabricated silicon. In: Proceedings. 34th international symposium on multiple-valued logic pp. 2\u20135.","DOI":"10.1109\/ISMVL.2004.1319911"},{"key":"e_1_3_5_477_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.12"},{"key":"e_1_3_5_478_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2022.3164338"},{"key":"e_1_3_5_479_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"e_1_3_5_480_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1975.1050654"},{"key":"e_1_3_5_481_1","doi-asserted-by":"crossref","unstructured":"Rupp K (2022) Microprocessor trend data.","DOI":"10.56553\/popets-2022-0080"},{"key":"e_1_3_5_482_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2301637"},{"key":"e_1_3_5_483_1","doi-asserted-by":"publisher","DOI":"10.1109\/16.766872"},{"key":"e_1_3_5_484_1","doi-asserted-by":"publisher","DOI":"10.1109\/16.249433"},{"key":"e_1_3_5_485_1","doi-asserted-by":"crossref","unstructured":"Salehian S Yan Y (2017) Evaluation of knight landing high bandwidth memory for HPC workloads. In: Proceedings of the seventh workshop on irregular applications: architectures and algorithms IA3\u201917. New York NY: Association for Computing Machinery pp. 1\u20134.","DOI":"10.1145\/3149704.3149766"},{"key":"e_1_3_5_486_1","unstructured":"Sanca V Ailamaki A (2023) Post-Moore\u2019s law fusion: high-bandwidth memory accelerators and native half-precision processing for CPU-local analytics. In: Joint workshops at 49th international conference on very large data bases (VLDBW\u201923) pp. 13."},{"key":"e_1_3_5_487_1","doi-asserted-by":"crossref","unstructured":"Sancho JC Lang M Kerbyson DJ (2010) Analyzing the trade-off between multiple memory controllers and memory channels on multi-core processor performance. In: 2010 IEEE international symposium on parallel & distributed processing workshops and Phd forum (IPDPSW) pp. 1\u20137.","DOI":"10.1109\/IPDPSW.2010.5470812"},{"key":"e_1_3_5_488_1","doi-asserted-by":"crossref","unstructured":"Saraswat K Cho H Kapur P et al. (2008) Performance comparison between copper carbon nanotube and optical interconnects. In: 2008 IEEE international symposium on circuits and systems (ISCAS) pp. 2781\u20132784.","DOI":"10.1109\/ISCAS.2008.4542034"},{"key":"e_1_3_5_489_1","doi-asserted-by":"crossref","unstructured":"Sarmah MJ Azeemuddin S (2014) A circuit to synchronize high speed serial communication channel. In: 2014 International conference on field-programmable technology (FPT) pp. 239\u2013242.","DOI":"10.1109\/FPT.2014.7082784"},{"issue":"12","key":"e_1_3_5_490_1","first-page":"1179","article-title":"A circuit to eliminate serial skew in high-speed serial communication channels","volume":"62","author":"Sarmah MJ","year":"2015","unstructured":"Sarmah MJ, Azeemuddin S (2015) A circuit to eliminate serial skew in high-speed serial communication channels. IEEE Transactions on Circuits and Systems II: Express Briefs 62(12): 1179\u20131183.","journal-title":"IEEE Transactions on Circuits and Systems II: Express Briefs"},{"key":"e_1_3_5_491_1","doi-asserted-by":"crossref","unstructured":"Sarmah MJ Azeemuddin S (2017) Circuits for initializing simplex communication channels. In: 2017 IEEE international conference on computational intelligence and computing research (ICCIC) pp. 1\u20134.","DOI":"10.1109\/ICCIC.2017.8524237"},{"key":"e_1_3_5_492_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSTQE.2015.2420991"},{"key":"e_1_3_5_493_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2002.1021941"},{"key":"e_1_3_5_494_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.642817"},{"key":"e_1_3_5_495_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-40047-6_56"},{"key":"e_1_3_5_496_1","doi-asserted-by":"crossref","unstructured":"Schrimpf RD Warren KM Weller RA et al. (2008) Reliability and radiation effects in IC technologies. In: 2008 IEEE international reliability physics symposium pp. 97\u2013106.","DOI":"10.1109\/RELPHY.2008.4558869"},{"key":"e_1_3_5_497_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.920069"},{"key":"e_1_3_5_498_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2009.9"},{"key":"e_1_3_5_499_1","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1993.tb00550.x"},{"key":"e_1_3_5_500_1","doi-asserted-by":"crossref","unstructured":"Shah K Mello M (2004) Ball grid array solder joint failure envelope development for dynamic loading. In: 2004 Proceedings. 54th Electronic components and technology conference (IEEE Cat. No.04CH37546) Vol. 1. pp. 1067\u20131074.","DOI":"10.1109\/ECTC.2004.1319472"},{"key":"e_1_3_5_501_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1985.1662802"},{"key":"e_1_3_5_502_1","doi-asserted-by":"crossref","unstructured":"Shahidi GG (2007) Evolution of CMOS technology at 32 nm and beyond. In: 2007 IEEE custom integrated circuits conference pp. 413\u2013416.","DOI":"10.1109\/CICC.2007.4405764"},{"key":"e_1_3_5_503_1","doi-asserted-by":"crossref","unstructured":"Shahzad H Sanaullah A Herbordt M (2021) Survey and future trends for FPGA cloud architectures. In: 2021 IEEE high performance extreme computing conference (HPEC) pp. 1\u201310.","DOI":"10.1109\/HPEC49654.2021.9622807"},{"key":"e_1_3_5_504_1","volume-title":"ISA System Architecture","author":"Shanley T","year":"1995","unstructured":"Shanley T, Anderson D, Swindle J, et al. (1995) ISA System Architecture. Mindshare PC System Architecture. Addison-Wesley."},{"key":"e_1_3_5_505_1","doi-asserted-by":"crossref","unstructured":"Shao YS Brooks D (2013) Energy characterization and instruction-level energy model of Intel\u2019s Xeon Phi processor. In: International symposium on low power electronics and design (ISLPED) pp. 389\u2013394.","DOI":"10.1109\/ISLPED.2013.6629328"},{"key":"e_1_3_5_506_1","doi-asserted-by":"crossref","unstructured":"Sharma A Bamiedakis N Karinou F et al. (2021) Multi-chiplet system architecture with shared uniform access memory based on board-level optical interconnects. In: 2021 Optical fiber communications conference and exhibition (OFC) pp. 1\u20133.","DOI":"10.1364\/OFC.2021.W6A.7"},{"key":"e_1_3_5_507_1","doi-asserted-by":"crossref","unstructured":"Shipman GM Swaminarayan S Grider G et al. (2022) Early performance results on 4th Gen Intel(R) Xeon (R) scalable processors with DDR and Intel(R) Xeon(R) processors codenamed sapphire rapids with HBM.","DOI":"10.2172\/1898330"},{"key":"e_1_3_5_508_1","doi-asserted-by":"publisher","DOI":"10.1002\/047122460X.ch1"},{"key":"e_1_3_5_509_1","doi-asserted-by":"crossref","unstructured":"Shorey AB Lu R (2016) Progress and application of through glass via (TGV) technology. In: 2016 Pan Pacific microelectronics symposium (Pan Pacific) pp. 1\u20136.","DOI":"10.1109\/PanPacific.2016.7428424"},{"key":"e_1_3_5_510_1","unstructured":"Sideco F (2023) Design once. Sell multiple times \u2013 AMD leveraging chiplets to execute on workload optimized processing strategy."},{"key":"e_1_3_5_511_1","doi-asserted-by":"crossref","unstructured":"Silva VRG Furtunato AFA Georgiou K et al. (2019) Energy-optimal configurations for single-node HPC applications. In: 2019 International conference on high performance computing & simulation (HPCS) pp. 448\u2013454.","DOI":"10.1109\/HPCS48598.2019.9188110"},{"key":"e_1_3_5_512_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.813345"},{"key":"e_1_3_5_513_1","doi-asserted-by":"crossref","unstructured":"Singh S Singh N (2016) Containers & Docker: emerging roles & future of Cloud technology. In: 2016 2nd International conference on applied and theoretical computing and communication technology (iCATccT) pp. 804\u2013807.","DOI":"10.1109\/ICATCCT.2016.7912109"},{"key":"e_1_3_5_514_1","doi-asserted-by":"crossref","unstructured":"Singhal S Gaur N Mehra A et al. (2015) Analysis and comparison of leakage power reduction techniques in CMOS circuits. In: 2015 2nd International conference on signal processing and integrated networks (SPIN) pp. 936\u2013944.","DOI":"10.1109\/SPIN.2015.7095351"},{"key":"e_1_3_5_515_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.476078"},{"key":"e_1_3_5_516_1","doi-asserted-by":"crossref","unstructured":"Smithson G (1998) Introduction to digital modulation schemes. In: IEE colloquium on the design of digital cellular handsets (Ref. No. 1998\/240) pp. 2\/1\u20132\/9.","DOI":"10.1049\/ic:19980230"},{"key":"e_1_3_5_517_1","doi-asserted-by":"crossref","unstructured":"Sodani A (2015) Knights landing (KNL): 2nd generation Intel\u00ae Xeon Phi processor. In: 2015 IEEE hot chips 27 symposium (HCS) pp. 1\u201324.","DOI":"10.1109\/HOTCHIPS.2015.7477467"},{"key":"e_1_3_5_518_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2016.25"},{"key":"e_1_3_5_519_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.563672"},{"key":"e_1_3_5_520_1","doi-asserted-by":"publisher","DOI":"10.1109\/JQE.1987.1073206"},{"key":"e_1_3_5_521_1","doi-asserted-by":"publisher","DOI":"10.1109\/JQE.1986.1073057"},{"key":"e_1_3_5_522_1","doi-asserted-by":"publisher","DOI":"10.1145\/358234.358246"},{"key":"e_1_3_5_523_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2018.2857470"},{"key":"e_1_3_5_524_1","doi-asserted-by":"crossref","unstructured":"Srinivasan V Brooks D Gschwind M et al. (2002) Optimizing pipelines for power and performance. In: 35th Annual IEEE\/ACM international symposium on microarchitecture 2002. (MICRO-35). Proceedings. pp. 333\u2013344.","DOI":"10.1109\/MICRO.2002.1176261"},{"key":"e_1_3_5_525_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11837-004-0285-1"},{"key":"e_1_3_5_526_1","unstructured":"Staff IRE (2019) One big wire change in \u201997 still helping chips achieve tiny scale."},{"key":"e_1_3_5_527_1","doi-asserted-by":"crossref","unstructured":"Stanley-Marbell P Cabezas VC Luijten RP (2011) Pinned to the walls \u2014 impact of packaging and application properties on the memory and power walls. In: IEEE\/ACM international symposium on low power electronics and design pp. 51\u201356.","DOI":"10.1109\/ISLPED.2011.5993603"},{"key":"e_1_3_5_528_1","doi-asserted-by":"crossref","unstructured":"Stanzione D Barth B Gaffney N et al. (2017) Stampede 2: the evolution of an XSEDE supercomputer. In: Proceedings of the practice and experience in advanced research computing 2017 on sustainability success and impact PEARC17. New York NY: Association for Computing Machinery pp. 1\u20138.","DOI":"10.1145\/3093338.3093385"},{"key":"e_1_3_5_529_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2017.02.002"},{"key":"e_1_3_5_530_1","doi-asserted-by":"crossref","unstructured":"Stoll C Gumhold S Seidel HP (2005) Visualization with stylized line primitives. In: VIS 05: IEEE visualization 2005 pp. 695\u2013702.","DOI":"10.1109\/VISUAL.2005.1532859"},{"key":"e_1_3_5_531_1","doi-asserted-by":"crossref","unstructured":"Su LT Naffziger S Papermaster M (2017) Multi-chip technologies to unleash computing performance gains over the next decade. In: 2017 IEEE international electron devices meeting (IEDM) pp. 1.1.1\u20131.1.8.","DOI":"10.1109\/IEDM.2017.8268306"},{"key":"e_1_3_5_532_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2974217"},{"key":"e_1_3_5_533_1","doi-asserted-by":"crossref","unstructured":"Sugimoto S Hayashi K Mano F (1989) Design of 2B1Q transceiver for ISDN subscriber loops. In: IEEE international conference on communications world prosperity through communications Vol.1 pp. 228\u2013232.","DOI":"10.1109\/ICC.1989.49698"},{"key":"e_1_3_5_534_1","doi-asserted-by":"crossref","unstructured":"Sumeet N Rawat K Nambiar M (2022) Performance evaluation of GraphCore IPU-M2000 accelerator for text detection application. In: Companion of the 2022 ACM\/SPEC international conference on performance engineering ICPE \u201922. New York NY: Association for Computing Machinery pp. 145\u2013152.","DOI":"10.1145\/3491204.3527469"},{"key":"e_1_3_5_535_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-79803-0_3"},{"key":"e_1_3_5_536_1","doi-asserted-by":"crossref","unstructured":"Sun Y Mukherjee S Baruah T et al. (2018) Evaluating performance tradeoffs on the radeon open compute platform. In: 2018 IEEE international symposium on performance analysis of systems and software (ISPASS) pp. 209\u2013218.","DOI":"10.1109\/ISPASS.2018.00034"},{"key":"e_1_3_5_537_1","unstructured":"Sun Y Agostini NB Dong S et al. (2020) Summarizing CPU and GPU design trends with product data."},{"key":"e_1_3_5_538_1","unstructured":"Sun PSV Titterton A Gopiani A et al. (2022a) Intelligence processing units accelerate neuromorphic learning."},{"key":"e_1_3_5_539_1","doi-asserted-by":"crossref","unstructured":"Sun Y Zheng L Wang Q et al. (2022b) Accelerating sparse deep neural network inference using GPU tensor cores. In: 2022 IEEE high performance extreme computing conference (HPEC) pp. 1\u20137.","DOI":"10.1109\/HPEC55821.2022.9926300"},{"key":"e_1_3_5_540_1","doi-asserted-by":"publisher","DOI":"10.1080\/09747338.1992.11436355"},{"key":"e_1_3_5_541_1","doi-asserted-by":"crossref","unstructured":"Suzuki O (2020) Recent advances in underfill for new package architectures. In: 2020 Pan Pacific microelectronics symposium (Pan Pacific) pp. 1\u20137.","DOI":"10.23919\/PanPacific48324.2020.9059466"},{"key":"e_1_3_5_542_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.970420"},{"key":"e_1_3_5_543_1","doi-asserted-by":"crossref","unstructured":"Sylvester D Keutzer K (1998) Getting to the bottom of deep submicron. In: 1998 IEEE\/ACM international conference on computer-aided design. Digest of technical papers (IEEE Cat. No.98CB36287) pp. 203\u2013211.","DOI":"10.1145\/288548.288614"},{"key":"e_1_3_5_544_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.828553"},{"key":"e_1_3_5_545_1","doi-asserted-by":"crossref","unstructured":"Sze V Chen YH Emer J et al. (2017) Hardware for machine learning: challenges and opportunities. In: 2017 IEEE custom integrated circuits conference (CICC) pp. 1\u20138.","DOI":"10.1109\/CICC.2017.7993626"},{"key":"e_1_3_5_546_1","doi-asserted-by":"crossref","unstructured":"Taka E Arora A Wu KC et al. (2023) MaxEVA: maximizing the efficiency of matrix multiplication on versal AI engine. In: 2023 International conference on field programmable technology (ICFPT) pp. 96\u2013105.","DOI":"10.1109\/ICFPT59805.2023.00016"},{"key":"e_1_3_5_547_1","doi-asserted-by":"crossref","unstructured":"Taka E Gourounas D Gerstlauer A et al. (2024) Efficient approaches for GEMM acceleration on leading AI-Optimized FPGAs. In: 2024 IEEE 32nd annual international symposium on field-programmable custom computing machines (FCCM) pp. 54\u201365.","DOI":"10.1109\/FCCM60383.2024.00015"},{"key":"e_1_3_5_548_1","doi-asserted-by":"crossref","unstructured":"Taka E Huang NC Chang CC et al. (2025) Systolic sparse tensor slices: FPGA building blocks for sparse and dense AI acceleration. In: Proceedings of the 2025 ACM\/SIGDA international symposium on field programmable gate arrays FPGA \u201925. New York NY: Association for Computing Machinery pp. 159\u2013171.","DOI":"10.1145\/3706628.3708867"},{"key":"e_1_3_5_549_1","doi-asserted-by":"crossref","unstructured":"Takahashi S Horiuchi K Tatsukoshi K et al. (2013) Development of through glass via (TGV) formation technology using electrical discharging for 2.5\/3D integrated packaging. In: 2013 IEEE 63rd electronic components and technology conference pp. 348\u2013352.","DOI":"10.1109\/ECTC.2013.6575594"},{"key":"e_1_3_5_550_1","doi-asserted-by":"crossref","unstructured":"Talpes E Williams D Sarma DD (2022) Dojo: the microarchitecture of tesla\u2019s exa-scale computer. In: 2022 IEEE Hot Chips 34 Symposium (HCS) pp. 1\u201328.","DOI":"10.1109\/HCS55958.2022.9895534"},{"key":"e_1_3_5_551_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2023.3258906"},{"key":"e_1_3_5_552_1","doi-asserted-by":"crossref","unstructured":"Tam SM Muljono H Huang M et al. (2018) SkyLake-SP: a 14nm 28-Core xeon\u00ae processor. In: 2018 IEEE international solid - state circuits conference - (ISSCC) pp. 34\u201336.","DOI":"10.1109\/ISSCC.2018.8310170"},{"key":"e_1_3_5_553_1","doi-asserted-by":"crossref","unstructured":"Tamitani I Ohta M Nomura M et al. (1992) An encoder\/decoder chip set for the MPEG video standard. In: Acoustics speech and signal processing IEEE international conference on Volume 5. Los Alamitos CA: IEEE Computer Society pp. 661\u2013664.","DOI":"10.1109\/ICASSP.1992.226509"},{"key":"e_1_3_5_554_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.parco.2014.09.001"},{"key":"e_1_3_5_555_1","doi-asserted-by":"crossref","unstructured":"Tan C Xie C Li A et al. (2021) AURORA: automated refinement of coarse-grained reconfigurable accelerators. In: 2021 Design automation & test in Europe conference & exhibition (DATE) pp. 1388\u20131393.","DOI":"10.23919\/DATE51398.2021.9473955"},{"key":"e_1_3_5_556_1","doi-asserted-by":"crossref","unstructured":"Taur Y (1999a) CMOS scaling beyond 0.1\/spl mu\/m: how far can it go? In: 1999 International symposium on VLSI technology systems and applications. Proceedings of technical papers. (Cat. No.99TH8453). pp. 6\u20139.","DOI":"10.1109\/VTSA.1999.785986"},{"key":"e_1_3_5_557_1","doi-asserted-by":"publisher","DOI":"10.1109\/6.774961"},{"key":"e_1_3_5_558_1","doi-asserted-by":"crossref","unstructured":"Taylor MB (2012) Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse. In: Proceedings of the 49th annual design automation conference DAC \u201912. New York NY: Association for Computing Machinery pp. 1131\u20131136.","DOI":"10.1145\/2228360.2228567"},{"key":"e_1_3_5_559_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2013.90"},{"key":"e_1_3_5_560_1","first-page":"84","volume-title":"Digital Transmission","author":"Teixeira M","year":"2007","unstructured":"Teixeira M, Zaharov V (2007) Digital Transmission. Chapter 7. John Wiley & Sons, Ltd, pp. 84\u2013101."},{"key":"e_1_3_5_561_1","doi-asserted-by":"crossref","unstructured":"Teshima M Kobayashi S Yamamoto T et al. (2008) Bit-error-tolerant (512*N)B\/(513*N+1)B code for 40Gb\/s and 100Gb\/s ethernet transport. In: IEEE INFOCOM workshops 2008 pp. 1\u20136.","DOI":"10.1109\/INFOCOM.2008.4544637"},{"key":"e_1_3_5_562_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.443.0379"},{"key":"e_1_3_5_563_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCSE.2017.29"},{"key":"e_1_3_5_564_1","doi-asserted-by":"publisher","DOI":"10.1016\/B978-0-8155-1594-4.00005-X"},{"key":"e_1_3_5_565_1","doi-asserted-by":"crossref","unstructured":"Tiwari V Singh D Rajgopal S et al. (1998) Reducing power in high-performance microprocessors. In: Proceedings of the 35th annual design automation conference DAC \u201998. New York NY: Association for Computing Machinery pp. 732\u2013737.","DOI":"10.1145\/277044.277227"},{"key":"e_1_3_5_566_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2017.2689538"},{"key":"e_1_3_5_567_1","doi-asserted-by":"crossref","unstructured":"T\u0151kei Z Ciofi I Roussel P et al. (2016) On-chip interconnect trends challenges and solutions: how to keep RC and reliability under control. In: 2016 IEEE symposium on VLSI technology pp. 1\u20132.","DOI":"10.1109\/VLSIT.2016.7573426"},{"key":"e_1_3_5_568_1","doi-asserted-by":"crossref","unstructured":"Tong JG Anderson IDL Khalid MAS (2006) Soft-core processors for embedded systems. In: 2006 International conference on microelectronics pp. 170\u2013173.","DOI":"10.1109\/ICM.2006.373294"},{"key":"e_1_3_5_569_1","doi-asserted-by":"crossref","unstructured":"Tonietto D (2022) The future of short reach interconnect. In: ESSCIRC 2022- IEEE 48th European solid state circuits conference (ESSCIRC) pp. 1\u20138.","DOI":"10.1109\/ESSCIRC55480.2022.9911398"},{"key":"e_1_3_5_570_1","unstructured":"Trader T (2017) Graphcore readies launch of 16nm Colossus-IPU chip."},{"key":"e_1_3_5_571_1","doi-asserted-by":"crossref","unstructured":"Tukanov N Srinivasaraghavan R Moreira JE et al. (2022) Modeling matrix engines for portability and performance. In: 2022 IEEE international parallel and distributed processing symposium (IPDPS) pp. 1173\u20131183.","DOI":"10.1109\/IPDPS53621.2022.00117"},{"key":"e_1_3_5_572_1","doi-asserted-by":"publisher","DOI":"10.1080\/00207217.2017.1285436"},{"key":"e_1_3_5_573_1","doi-asserted-by":"publisher","DOI":"10.1109\/COMST.2014.2361754"},{"key":"e_1_3_5_574_1","doi-asserted-by":"publisher","DOI":"10.1109\/MMM.2019.2909517"},{"key":"e_1_3_5_575_1","doi-asserted-by":"publisher","DOI":"10.1145\/358923.358939"},{"key":"e_1_3_5_576_1","doi-asserted-by":"crossref","unstructured":"Vanna-Iampikul P Zhu L Erdogan S et al. (2023) Glass interposer integration of logic and memory chiplets: PPA and power\/signal integrity benefits. In: 2023 60th ACM\/IEEE design automation conference (DAC) pp. 1\u20136.","DOI":"10.1109\/DAC56929.2023.10247949"},{"key":"e_1_3_5_577_1","doi-asserted-by":"crossref","unstructured":"Vasilakis E Sourdis I Papaefstathiou V et al. (2017) Modeling energy-performance tradeoffs in ARM big.LITTLE architectures. In: 2017 27th International symposium on power and timing modeling optimization and simulation (PATMOS) pp. 1\u20138.","DOI":"10.1109\/PATMOS.2017.8106950"},{"key":"e_1_3_5_578_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052168"},{"key":"e_1_3_5_579_1","doi-asserted-by":"publisher","DOI":"10.1186\/s11671-019-3046-3"},{"key":"e_1_3_5_580_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1269022"},{"key":"e_1_3_5_581_1","doi-asserted-by":"crossref","unstructured":"V\u00e9stias M Neto H (2014) Trends of CPU GPU and FPGA for high-performance computing. In: 2014 24th International conference on field programmable logic and applications (FPL) pp. 1\u20136.","DOI":"10.1109\/FPL.2014.6927483"},{"key":"e_1_3_5_582_1","doi-asserted-by":"crossref","unstructured":"Vidya S Kamat SV Khan A et al. (2018) 3D FinFET for next generation nano devices. In: 2018 International conference on current trends towards converging technologies (ICCTCT) pp. 1\u20139.","DOI":"10.1109\/ICCTCT.2018.8550967"},{"key":"e_1_3_5_583_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2976067"},{"key":"e_1_3_5_584_1","doi-asserted-by":"publisher","DOI":"10.1145\/106973.106991"},{"key":"e_1_3_5_585_1","doi-asserted-by":"crossref","unstructured":"Wang F Agrawal VD (2008) Single event upset: an embedded tutorial. In: 21st International conference on VLSI design (VLSID 2008) pp. 429\u2013434.","DOI":"10.1109\/VLSI.2008.28"},{"key":"e_1_3_5_586_1","unstructured":"Wang S Kanwar P (2019) BFloat16: the secret to high performance on Cloud TPUs. Google Cloud Blog 4."},{"key":"e_1_3_5_587_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2013.74"},{"key":"e_1_3_5_588_1","doi-asserted-by":"crossref","unstructured":"Wang Q Hua S Wang D (2010) A 1.1 GHz 8B\/10B encoder and decoder design. In: 2010 Asia Pacific conference on postgraduate research in microelectronics and electronics (PrimeAsia) pp. 138\u2013141.","DOI":"10.1109\/PRIMEASIA.2010.5604943"},{"key":"e_1_3_5_589_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-06486-4"},{"key":"e_1_3_5_590_1","unstructured":"Wang N Choi J Brand D et al. (2018) Training deep neural networks with 8-Bit floating point numbers. In: Proceedings of the 32nd international conference on neural information processing systems NIPS\u201918. Red Hook NY: Curran Associates Inc. pp. 7686\u20137695."},{"key":"e_1_3_5_591_1","doi-asserted-by":"crossref","unstructured":"Wang Z Huang H Zhang J et al. (2020) Shuhai: benchmarking high bandwidth memory on FPGAS. In: 2020 IEEE 28th annual international symposium on field-programmable custom computing machines (FCCM) pp. 111\u2013119.","DOI":"10.1109\/FCCM48280.2020.00024"},{"key":"e_1_3_5_592_1","doi-asserted-by":"publisher","DOI":"10.1080\/01457630701686727"},{"key":"e_1_3_5_593_1","doi-asserted-by":"crossref","unstructured":"Wei L Chen Z Johnson M et al. (1998) Design and optimization of low voltage high performance dual threshold CMOS circuits. In: Proceedings of the 35th annual design automation conference DAC \u201998. New York NY: Association for Computing Machinery pp. 489\u2013494.","DOI":"10.1145\/277044.277179"},{"key":"e_1_3_5_594_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3228860"},{"key":"e_1_3_5_595_1","doi-asserted-by":"crossref","unstructured":"Weng PY Chen CH Chen CH et al. (2018) Factors affecting near-end crosstalk (NEXT) in high speed serial links. In: 2018 15th international conference on electromagnetic interference & compatibility (INCEMIC) pp. 1\u20134.","DOI":"10.1109\/INCEMIC.2018.8704575"},{"key":"e_1_3_5_596_1","doi-asserted-by":"crossref","unstructured":"Weng PY Chen CH Chen J et al. (2021) Eye comparison between unencoded and 128b\/130b-encoded NRZ signals. In: 2021 IEEE 30th conference on electrical performance of electronic packaging and systems (EPEPS) pp. 1\u20133.","DOI":"10.1109\/EPEPS51341.2021.9609173"},{"key":"e_1_3_5_597_1","doi-asserted-by":"publisher","DOI":"10.1145\/3131346"},{"key":"e_1_3_5_598_1","volume-title":"CMOS VLSI Design: A Circuits and Systems Perspective","author":"Weste N","year":"2010","unstructured":"Weste N, Harris D (2010) CMOS VLSI Design: A Circuits and Systems Perspective. 4th edition. Addison-Wesley Publishing Company.","edition":"4"},{"key":"e_1_3_5_599_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3132551"},{"key":"e_1_3_5_600_1","doi-asserted-by":"publisher","DOI":"10.1109\/JLT.2012.2212180"},{"key":"e_1_3_5_601_1","doi-asserted-by":"publisher","DOI":"10.1109\/6144.759349"},{"key":"e_1_3_5_602_1","doi-asserted-by":"crossref","unstructured":"Wu KC Tsai YW (2004) Structured ASIC evolution or revolution? In: Proceedings of the 2004 international symposium on physical design ISPD \u201904. New York NY: Association for Computing Machinery pp. 103\u2013106.","DOI":"10.1145\/981066.981088"},{"key":"e_1_3_5_603_1","doi-asserted-by":"crossref","unstructured":"Wu Q Xu J Li X et al. (2009) The research and implementation of interfacing based on PCI express. In: 2009 9th International conference on electronic measurement & instruments pp. 3\u2013116\u20133\u2013121.","DOI":"10.1109\/ICEMI.2009.5274345"},{"key":"e_1_3_5_604_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEMC.2013.2257796"},{"key":"e_1_3_5_605_1","doi-asserted-by":"crossref","unstructured":"Wu Z Zhang C Li F et al. (2016) High speed serial interface transceiver controller based on JESD204B. In: 2016 14th IEEE international new circuits and systems conference (NEWCAS) pp. 1\u20134.","DOI":"10.1109\/NEWCAS.2016.7604778"},{"key":"e_1_3_5_606_1","volume-title":"Digital Modulation Techniques","author":"Xiong F","year":"2006","unstructured":"Xiong F (2006) Digital Modulation Techniques. 2nd edition. Artech House, Inc.","edition":"2"},{"key":"e_1_3_5_607_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2017.2689519"},{"key":"e_1_3_5_608_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2018.2882285"},{"key":"e_1_3_5_609_1","doi-asserted-by":"crossref","unstructured":"Xu C Chen X Dick RP et al. (2010) Cache contention and application performance prediction for multi-core systems. In: 2010 IEEE international symposium on performance analysis of systems & software (ISPASS) pp. 76\u201386.","DOI":"10.1109\/ISPASS.2010.5452065"},{"key":"e_1_3_5_610_1","doi-asserted-by":"publisher","DOI":"10.3390\/mi13071148"},{"key":"e_1_3_5_611_1","volume-title":"logi3D Scalable 3D Graphic Accelerator. Datasheet","author":"Xylon doo","year":"2021","unstructured":"Xylon doo (2021) logi3D Scalable 3D Graphic Accelerator. Datasheet. Xylon D.O.O."},{"key":"e_1_3_5_612_1","doi-asserted-by":"publisher","DOI":"10.1109\/101.583610"},{"key":"e_1_3_5_613_1","doi-asserted-by":"crossref","unstructured":"Yeoh HP Lii MJ Sankman B et al. (2000) Flip chip pin grid array (FC-PGA) packaging technology. In: Proceedings of 3rd electronics packaging technology conference (EPTC 2000) (Cat. No.00EX456) pp. 33\u201340.","DOI":"10.1109\/EPTC.2000.906346"},{"key":"e_1_3_5_614_1","doi-asserted-by":"crossref","unstructured":"Yoon SW Ku JH Suthiwongsunthorn N et al. (2009) Fabrication and packaging of microbump interconnections for 3D TSV. In: 2009 IEEE international conference on 3D system integration pp. 1\u20135.","DOI":"10.1109\/3DIC.2009.5306554"},{"key":"e_1_3_5_615_1","doi-asserted-by":"crossref","unstructured":"Yue P Shekhar S (2022) F4: paving the way to 200Gb\/s transceivers. In: 2022 IEEE international solid- state circuits conference (ISSCC) 65 pp. 537\u2013539.","DOI":"10.1109\/ISSCC42614.2022.9731799"},{"key":"e_1_3_5_616_1","doi-asserted-by":"crossref","unstructured":"Zahiri B (2003) Structured ASICs: opportunities and challenges. In: Proceedings 21st international conference on computer design San Jose CA 13\u201315 October 2003 pp. 404\u2013409.","DOI":"10.1109\/ICCD.2003.1240929"},{"key":"e_1_3_5_617_1","doi-asserted-by":"crossref","unstructured":"Zhang HY Zhang XW Lau BL et al. (2013) Thermal characterization and simulation study of 2.5D packages with multi-chip module on through silicon interposer. In: 2013 IEEE 15th electronics packaging technology conference (EPTC 2013) Piscataway NJ 11\u201313 December 2013 pp. 363\u2013368.","DOI":"10.1109\/EPTC.2013.6745743"},{"key":"e_1_3_5_618_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2026162"},{"key":"e_1_3_5_619_1","doi-asserted-by":"crossref","unstructured":"Zheng H Lin J Zhang Z et al. (2008) Mini-rank: adaptive DRAM architecture for improving memory power efficiency. In: 2008 41st IEEE\/ACM international symposium on microarchitecture Lake Como Italy 8\u201312 November 2008 pp. 210\u2013221.","DOI":"10.1109\/MICRO.2008.4771792"},{"key":"e_1_3_5_620_1","doi-asserted-by":"crossref","unstructured":"Zhou D Preparata F Kang S (1988) Interconnection delay in very high-speed VLSI. In: Proceedings 1988 IEEE international conference on computer design: VLSI Rye Brook NY 03\u201305 October 1988 pp. 52\u201355.","DOI":"10.1109\/ICCD.1988.25658"},{"key":"e_1_3_5_621_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2019.2910068"},{"key":"e_1_3_5_622_1","doi-asserted-by":"publisher","DOI":"10.1186\/s43593-022-00027-x"},{"key":"e_1_3_5_623_1","doi-asserted-by":"crossref","unstructured":"Zhuang B Liu J Pan Z et al. (2023a) A survey on efficient training of transformers.","DOI":"10.24963\/ijcai.2023\/764"},{"key":"e_1_3_5_624_1","doi-asserted-by":"crossref","unstructured":"Zhuang J Lau J Ye H et al. (2023b) CHARM: composing heterogeneous accelerators for matrix multiply on versal ACAP architecture. In: Proceedings of the 2023 ACM\/SIGDA international symposium on field programmable gate arrays FPGA \u201923. New York NY: Association for Computing Machinery pp. 153\u2013164.","DOI":"10.1145\/3543622.3573210"},{"key":"e_1_3_5_625_1","doi-asserted-by":"crossref","unstructured":"Zhuravlev S Blagodurov S Fedorova A (2010) Addressing shared resource contention in multicore processors via scheduling. In: Proceedings of the fifteenth international conference on architectural support for programming languages and operating systems ASPLOS XV. New York NY: Association for Computing Machinery pp. 129\u2013142.","DOI":"10.1145\/1736020.1736036"},{"key":"e_1_3_5_626_1","doi-asserted-by":"crossref","unstructured":"Zyuban V Kogge P (2000) Optimization of high-performance superscalar architectures for energy efficiency. In: ISLPED\u201900: Proceedings of the 2000 international symposium on low power electronics and design (Cat. No.00TH8514) Rapallo Italy 26\u201327 July 2000 pp. 84\u201389.","DOI":"10.1109\/LPE.2000.155258"},{"key":"e_1_3_5_627_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.910816"}],"container-title":["The International Journal of High Performance Computing Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.1177\/10943420251348799","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/journals.sagepub.com\/doi\/full-xml\/10.1177\/10943420251348799","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.1177\/10943420251348799","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T21:48:40Z","timestamp":1781905720000},"score":1,"resource":{"primary":{"URL":"https:\/\/journals.sagepub.com\/doi\/10.1177\/10943420251348799"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,12,16]]},"references-count":626,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2026,7]]}},"alternative-id":["10.1177\/10943420251348799"],"URL":"https:\/\/doi.org\/10.1177\/10943420251348799","relation":{},"ISSN":["1094-3420","1741-2846"],"issn-type":[{"value":"1094-3420","type":"print"},{"value":"1741-2846","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,12,16]]}}}