{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,2]],"date-time":"2026-05-02T04:44:05Z","timestamp":1777697045238,"version":"3.51.4"},"reference-count":32,"publisher":"SAGE Publications","issue":"6","license":[{"start":{"date-parts":[[2025,8,26]],"date-time":"2025-08-26T00:00:00Z","timestamp":1756166400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/journals.sagepub.com\/page\/policies\/text-and-data-mining-license"}],"content-domain":{"domain":["journals.sagepub.com"],"crossmark-restriction":true},"short-container-title":["Intelligent Decision Technologies"],"published-print":{"date-parts":[[2025,11]]},"abstract":"<jats:p>The paper explores low-power design strategies for SRAM cells in wearable and implantable devices (WIDs) to address critical power limitations that hinder further miniaturization. FinFET solves the problem of leakage current (I_Leakage) by improving the challenging power versus performance trade-off. This research develops 7-Transistor SRAM cells based on FinFETs using the Multi Threshold CMOS (MTCMOS) and Upper Self Controllable Voltage Level (USVL) methods. Using 45\u2005nm FinFET technologies, the design and simulation of all design circuits are carried out with Cadence Virtuoso. The work adopts a multi-disciplinary approach, combining device-circuit co-design to achieve ultra-low-power operations suitable for complex tasks in wearable and implantable micro systems. The proposed design shows that the USVL method of a 7T SRAM using FinFET is more effective than the MTCMOS methodology in terms of leakage power and leakage currents. Additionally, among other proposed approaches, a comparative analysis of leakage currents and leakage power is conducted. Key outcomes include significant improvements in leakage power through FinFET-based SRAM cell using USVL technique. This paper contributes to advancing low-leakage wearable\/ implantable devices (WIDs) by integrating innovative leakage reduction techniques with cutting-edge low-power circuit designs. The proposed design achieves a minimum leakage current of 10.6\u2005nA and leakage power of 26.98\u2005nW by utilizing USVL approach. Compared to SRAM cells designed with the MTCMOS technique, the proposed method results in approximately 17.8% and 28% reduction in leakage power and leakage current, respectively. The findings pave the way for developing smaller, smarter, and sustainable wearable and implantable devices capable of complex tasks without reliance on batteries.<\/jats:p>","DOI":"10.1177\/18724981251370447","type":"journal-article","created":{"date-parts":[[2025,8,26]],"date-time":"2025-08-26T12:57:42Z","timestamp":1756213062000},"page":"4297-4309","update-policy":"https:\/\/doi.org\/10.1177\/sage-journals-update-policy","source":"Crossref","is-referenced-by-count":3,"title":["Energy efficient memory architectures for next-generation wearable healthcare devices"],"prefix":"10.1177","volume":"19","author":[{"given":"Deepak","family":"Garg","sequence":"first","affiliation":[{"name":"Department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Delhi-NCR Campus, Ghaziabad, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Devendra Kumar","family":"Sharma","sequence":"additional","affiliation":[{"name":"University of Malta"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3868-0481","authenticated-orcid":false,"given":"Lalit","family":"Garg","sequence":"additional","affiliation":[{"name":"University of Malta"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"179","published-online":{"date-parts":[[2025,8,26]]},"reference":[{"key":"e_1_3_3_2_2","volume-title":"Low-power VLSI circuits and systems","author":"Pal A","year":"2014","unstructured":"Pal A. Low-power VLSI circuits and systems. New Delhi, India: Springer, 2014."},{"key":"e_1_3_3_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2014.2362307"},{"key":"e_1_3_3_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/JBHI.2014.2366125"},{"key":"e_1_3_3_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.58"},{"key":"e_1_3_3_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2144450"},{"key":"e_1_3_3_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2813326"},{"key":"e_1_3_3_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2332267"},{"key":"e_1_3_3_9_2","first-page":"46","volume-title":"What is killing Moore's law? Challenges in advanced FinFET technology integration","author":"Malinowski A","unstructured":"Malinowski A, Chen J, Mishra SK, et al. What is killing Moore's law? Challenges in advanced FinFET technology integration. In: 2019 MIXDES-26th International Conference\u201d Mixed Design of Integrated Circuits and Systems\u201d, 2019, June, pp.46\u201351: IEEE."},{"key":"e_1_3_3_10_2","doi-asserted-by":"publisher","DOI":"10.37391\/ijeer.100253"},{"key":"e_1_3_3_11_2","unstructured":"International Roadmap for Device and Systems (IRDS) 2022. Available online: https:\/\/irds.ieee.org\/editions\/2022 (accessed on 15 April 2023)."},{"key":"e_1_3_3_12_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.spmi.2015.06.004"},{"key":"e_1_3_3_13_2","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea8040041"},{"key":"e_1_3_3_14_2","first-page":"247","volume-title":"Low power 8T SRAM using 32nm independent gate FinFET technology","author":"Kim YB","unstructured":"Kim YB, Kim YB, Lombardi F. Low power 8T SRAM using 32nm independent gate FinFET technology. In: 2008 IEEE International SOC Conference, 2008, September, pp.247\u2013250: IEEE."},{"key":"e_1_3_3_15_2","doi-asserted-by":"publisher","DOI":"10.1007\/s12633-021-01366-z"},{"key":"e_1_3_3_16_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.procs.2020.04.157"},{"key":"e_1_3_3_17_2","first-page":"1","volume-title":"Circuit design in nano-scale CMOS technologies","author":"Zhang K","unstructured":"Zhang K. Circuit design in nano-scale CMOS technologies. In: 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) IEEE, 2018, pp.1\u20134."},{"key":"e_1_3_3_18_2","first-page":"1","volume-title":"TFET And FinFET hybrid technologies for SRAM cell: performance improvement over a large VDD-range","author":"Liautard R","unstructured":"Liautard R, Trojman L, Arevalo A, et al. TFET And FinFET hybrid technologies for SRAM cell: performance improvement over a large VDD-range. In: 2019 IEEE Fourth Ecuador Technical Chapters Meeting (ETCM), 2019, pp.1\u20135: IEEE."},{"key":"e_1_3_3_19_2","doi-asserted-by":"publisher","DOI":"10.29292\/jics.v14i2.57"},{"key":"e_1_3_3_20_2","doi-asserted-by":"publisher","DOI":"10.1108\/CW-12-2018-0098"},{"key":"e_1_3_3_21_2","first-page":"157","article-title":"A comprehensive survey on the internet of things (IoT) in healthcare","author":"Garg D","year":"2022","unstructured":"Garg D, Sharma DK, Mani P, et al. A comprehensive survey on the internet of things (IoT) in healthcare. Role Internet Things (IoT) Biomed Eng 2022: 157\u2013184.","journal-title":"Role Internet Things (IoT) Biomed Eng"},{"key":"e_1_3_3_22_2","doi-asserted-by":"publisher","DOI":"10.1201\/9781003361633-1"},{"key":"e_1_3_3_23_2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2169678"},{"key":"e_1_3_3_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2156435"},{"key":"e_1_3_3_25_2","first-page":"63","volume-title":"An independent-gate FinFET SRAM cell for high data stability and enhanced integration density","author":"Liu Z","unstructured":"Liu Z, Tawfik SA, Kursun V. An independent-gate FinFET SRAM cell for high data stability and enhanced integration density. In: Proceedings of the IEEE International SOC Conference, HsinChu, Taiwan, 26\u201329 September 2007, pp.63\u201366."},{"key":"e_1_3_3_26_2","doi-asserted-by":"publisher","DOI":"10.1080\/00207217.2023.2238326"},{"key":"e_1_3_3_27_2","first-page":"1","volume-title":"17.1 A 0.6 v 1.5GHz 84 Mb SRAM design in 14nm FinFET CMOS technology","author":"Karl E","unstructured":"Karl E, Guo Z, Conary JW, et al. 17.1 A 0.6 v 1.5GHz 84 Mb SRAM design in 14nm FinFET CMOS technology. In: 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of Technical Papers, 2015, February, pp.1\u20133: IEEE."},{"key":"e_1_3_3_28_2","first-page":"747","volume-title":"Schmitt trigger leakage reduction using MTCMOS technique at 45-nm technology","author":"Garg D","unstructured":"Garg D, Sharma DK. Schmitt trigger leakage reduction using MTCMOS technique at 45-nm technology. In: International Conference on Micro-Electronics and Telecommunication Engineering, 2023, September, pp.747\u2013753. Singapore: Springer Nature Singapore."},{"key":"e_1_3_3_29_2","first-page":"478","volume-title":"Analysis of low power 7T SRAM cell employing improved SVL (ISVL) technique2017 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT)","author":"Kumar CSH","unstructured":"Kumar CSH, Kariyappa BS. Analysis of low power 7T SRAM cell employing improved SVL (ISVL) technique. In: 2017 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), 2017, pp.478\u2013482. Available from: https:\/\/doi.org\/10.1109\/ICEECCOT. 2017.8284551."},{"key":"e_1_3_3_30_2","doi-asserted-by":"publisher","DOI":"10.1007\/s12633-021-01290-2"},{"key":"e_1_3_3_31_2","first-page":"202","volume-title":"Characterization of a novel low leakage power and area efficient 7T SRAM cell","author":"Venkatareddy A","unstructured":"Venkatareddy A, Sithara R, Nithin Kumar YB, et al. Characterization of a novel low leakage power and area efficient 7T SRAM cell. In: 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), Kolkata, India, 2016, pp.202\u2013206."},{"key":"e_1_3_3_32_2","doi-asserted-by":"publisher","DOI":"10.3103\/S0735272714090015"},{"key":"e_1_3_3_33_2","first-page":"1","volume-title":"Design of 7T FinFET based SRAM cell design for nanometer regime","author":"Sneha G","unstructured":"Sneha G, Krishna BH, Kumar CA. Design of 7T FinFET based SRAM cell design for nanometer regime. In: 2017 International Conference on Inventive Systems and Control (ICISC), Coimbatore, India, 2017, pp.1\u20134."}],"container-title":["Intelligent Decision Technologies"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.1177\/18724981251370447","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/journals.sagepub.com\/doi\/full-xml\/10.1177\/18724981251370447","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.1177\/18724981251370447","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,4,29]],"date-time":"2026-04-29T09:21:41Z","timestamp":1777454501000},"score":1,"resource":{"primary":{"URL":"https:\/\/journals.sagepub.com\/doi\/10.1177\/18724981251370447"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,8,26]]},"references-count":32,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2025,11]]}},"alternative-id":["10.1177\/18724981251370447"],"URL":"https:\/\/doi.org\/10.1177\/18724981251370447","relation":{},"ISSN":["1872-4981","1875-8843"],"issn-type":[{"value":"1872-4981","type":"print"},{"value":"1875-8843","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,8,26]]}}}