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In this paper, an approach that provides a promising solution for energy reduction is proposed, by using a micro-architectural technique referred to as variable stage pipelining, which can be further validated and extended to different application domains such as mobile and desktop. An analytical model for evaluating the relationship between the number of cores and the pipeline stage depth in a chip multi-processor is also proposed, based on which the optimal pipeline depth for various metrics are calculated.<\/jats:p>","DOI":"10.1186\/s13673-015-0046-x","type":"journal-article","created":{"date-parts":[[2015,9,21]],"date-time":"2015-09-21T13:26:32Z","timestamp":1442841992000},"update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":6,"title":["An energy-delay product study on chip multi-processors for variable stage pipelining"],"prefix":"10.1186","volume":"5","author":[{"given":"Vijayalakshmi","family":"Saravanan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alagan","family":"Anpalagan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Isaac","family":"Woungang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2015,9,21]]},"reference":[{"key":"46_CR1","unstructured":"Chakraborty K, Roy S (2012) Architecturally homogeneous power-performance heterogeneous multicore processor. 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