{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,29]],"date-time":"2026-05-29T05:01:48Z","timestamp":1780030908067,"version":"3.53.1"},"reference-count":43,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2026,5,29]],"date-time":"2026-05-29T00:00:00Z","timestamp":1780012800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"},{"start":{"date-parts":[[2026,5,29]],"date-time":"2026-05-29T00:00:00Z","timestamp":1780012800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key R&D Program of China","doi-asserted-by":"crossref","award":["2023YFA1009500"],"award-info":[{"award-number":["2023YFA1009500"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Research Project of Quancheng Laboratory","award":["QCL20250101"],"award-info":[{"award-number":["QCL20250101"]}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["2125204, 62372274, 62502275"],"award-info":[{"award-number":["2125204, 62372274, 62502275"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Cybersecurity"],"abstract":"<jats:title>Abstract<\/jats:title>\n                  <jats:p>Side-channel attacks pose a major threat to cryptographic implementations, as they can exploit physical leakages to recover secret information. Masking is one of the most widely adopted countermeasures, aiming to protect sensitive intermediate values by randomization. However, when deployed in hardware, masking faces the challenges from the glitch leakage, which can easily undermine the security integrity of masking techniques and affect the foundational independent assumptions upon which they are based. To address the intricacies of hardware implementation, circuit separation using registers has emerged as a straightforward method. In this paper, we investigate low-latency hardware masking by exploring the use of buffers (rather than registers) to prevent glitch propagation. Rather than directly inserting buffers into the circuit path, our approach involves employing a chain of buffers to generate signals that serve as controls, thereby synchronizing blocks that require sequential computation. This significantly reduces the power consumption of the shielding circuit while also decreasing latency within the circuit.<\/jats:p>","DOI":"10.1186\/s42400-026-00606-2","type":"journal-article","created":{"date-parts":[[2026,5,29]],"date-time":"2026-05-29T04:09:42Z","timestamp":1780027782000},"update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Hardware masking with buffer chain"],"prefix":"10.1186","volume":"9","author":[{"given":"Guofeng","family":"Qin","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yihao","family":"Zhu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chun","family":"Guo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bohan","family":"Wang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hao","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6982-2537","authenticated-orcid":false,"given":"Weijia","family":"Wang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2026,5,29]]},"reference":[{"key":"606_CR1","doi-asserted-by":"publisher","first-page":"5108","DOI":"10.1109\/TIFS.2021.3123527","volume":"16","author":"V Arribas","year":"2021","unstructured":"Arribas V, Zhang Z, Nikova S (2021) LLTI: low-latency threshold implementations. IEEE Trans Inf Forensics Secur 16:5108\u20135123","journal-title":"IEEE Trans Inf Forensics Secur"},{"key":"606_CR2","doi-asserted-by":"crossref","unstructured":"Bilgin B, Gierlichs B, Nikova S, et\u00a0al (2014) Higher-order threshold implementations. In: Sarkar P, Iwata T (eds) Advances in Cryptology - ASIACRYPT 2014 - 20th International Conference on the Theory and Application of Cryptology and Information Security, Kaoshiung, Taiwan, R.O.C., December 7-11, 2014, Proceedings, Part II, Lecture Notes in Computer Science, vol 8874. Springer, pp 326\u2013343","DOI":"10.1007\/978-3-662-45608-8_18"},{"issue":"2","key":"606_CR3","doi-asserted-by":"publisher","first-page":"280","DOI":"10.1007\/s00145-012-9124-7","volume":"26","author":"J Boyar","year":"2013","unstructured":"Boyar J, Matthews P, Peralta R (2013) Logic minimization techniques with applications to cryptology. J Cryptol 26(2):280\u2013312","journal-title":"J Cryptol"},{"key":"606_CR4","doi-asserted-by":"crossref","unstructured":"Canright D, Batina L (2009) A very compact \u201cperfectly masked\u201d s-box for AES (corrected). IACR Cryptol ePrint Arch pp 11","DOI":"10.1007\/978-3-540-68914-0_27"},{"issue":"2","key":"606_CR5","doi-asserted-by":"publisher","first-page":"136","DOI":"10.46586\/tches.v2021.i2.136-158","volume":"2021","author":"G Cassiers","year":"2021","unstructured":"Cassiers G, Standaert F (2021) Provably secure hardware masking in the transition- and glitch-robust probing model: better safe than sorry. IACR Trans Cryptogr Hardw Embed Syst 2021(2):136\u2013158","journal-title":"IACR Trans Cryptogr Hardw Embed Syst"},{"issue":"10","key":"606_CR6","doi-asserted-by":"publisher","first-page":"1677","DOI":"10.1109\/TC.2020.3022979","volume":"70","author":"G Cassiers","year":"2021","unstructured":"Cassiers G, Gr\u00e9goire B, Levi I et al (2021) Hardware private circuits: from trivial composition to full verification. IEEE Trans Comput 70(10):1677\u20131690","journal-title":"IEEE Trans Comput"},{"key":"#cr-split#-606_CR7.1","doi-asserted-by":"crossref","unstructured":"Chari S, Jutla CS, Rao JR, et\u00a0al (1999) Towards sound approaches to counteract power-analysis attacks. In: Wiener MJ","DOI":"10.1007\/3-540-48405-1_26"},{"key":"#cr-split#-606_CR7.2","unstructured":"(ed) Advances in Cryptology - CRYPTO '99, 19th Annual International Cryptology Conference, Santa Barbara, California, USA, August 15-19, 1999, Proceedings, Lecture Notes in Computer Science, vol 1666. Springer, pp 398-412"},{"key":"606_CR8","doi-asserted-by":"publisher","first-page":"329","DOI":"10.46586\/tches.v2024.i2.329-358","volume":"2","author":"H Cheng","year":"2024","unstructured":"Cheng H, Page D (2024) Wang W (2024) eliminate: a leakage-focused ISE for masked implementation. IACR Trans Cryptogr Hardw Embed Syst 2:329\u2013358","journal-title":"IACR Trans Cryptogr Hardw Embed Syst"},{"key":"606_CR9","doi-asserted-by":"crossref","unstructured":"Cnudde TD, Reparaz O, Bilgin B, et\u00a0al (2016) Masking AES with d+1 shares in hardware. In: Bilgin B, Nikova S, Rijmen V (eds) Proceedings of the ACM Workshop on Theory of Implementation Security, TIS@CCS 2016 Vienna, Austria, October, 2016. ACM, p\u00a043","DOI":"10.1145\/2996366.2996428"},{"key":"606_CR10","doi-asserted-by":"crossref","unstructured":"Coron J, Greuet A, Zeitoun R (2020) Side-channel masking with pseudo-random generator. In: Canteaut A, Ishai Y (eds) Advances in Cryptology - EUROCRYPT 2020 - 39th Annual International Conference on the Theory and Applications of Cryptographic Techniques, Zagreb, Croatia, May 10-14, 2020, Proceedings, Part III, Lecture Notes in Computer Science, vol 12107. Springer, pp 342\u2013375","DOI":"10.1007\/978-3-030-45727-3_12"},{"key":"606_CR11","doi-asserted-by":"crossref","unstructured":"Cui S, Balasch J (2023) Efficient software masking of AES through instruction set extensions. In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023. IEEE, pp 1\u20136","DOI":"10.23919\/DATE56975.2023.10137150"},{"key":"606_CR12","doi-asserted-by":"crossref","unstructured":"Faust S, Paglialonga C, Schneider T (2017) Amortizing randomness complexity in private circuits. In: Takagi T, Peyrin T (eds) Advances in Cryptology - ASIACRYPT 2017 - 23rd International Conference on the Theory and Applications of Cryptology and Information Security, Hong Kong, China, December 3-7, 2017, Proceedings, Part I, Lecture Notes in Computer Science, vol 10624. Springer, pp 781\u2013810","DOI":"10.1007\/978-3-319-70694-8_27"},{"issue":"2","key":"606_CR13","doi-asserted-by":"publisher","first-page":"73","DOI":"10.46586\/tches.v2020.i2.73-98","volume":"2020","author":"S Gao","year":"2020","unstructured":"Gao S, Marshall B, Page D et al (2020) FENL: an ISE to mitigate analogue micro-architectural leakage. IACR Trans Cryptogr Hardw Embed Syst 2020(2):73\u201398","journal-title":"IACR Trans Cryptogr Hardw Embed Syst"},{"issue":"4","key":"606_CR14","doi-asserted-by":"publisher","first-page":"283","DOI":"10.46586\/tches.v2021.i4.283-325","volume":"2021","author":"S Gao","year":"2021","unstructured":"Gao S, Gro\u00dfsch\u00e4dl J, Marshall B et al (2021) An instruction set extension to support software-based masking. IACR Trans Cryptogr Hardw Embed Syst 2021(4):283\u2013325","journal-title":"IACR Trans Cryptogr Hardw Embed Syst"},{"key":"606_CR15","doi-asserted-by":"crossref","unstructured":"Ghoshal A, Cnudde TD (2017) Several masked implementations of the boyar-peralta AES s-box. In: Patra A, Smart NP (eds) Progress in Cryptology - INDOCRYPT 2017 - 18th International Conference on Cryptology in India, Chennai, India, December 10-13, 2017, Proceedings, Lecture Notes in Computer Science, vol 10698. Springer, pp 384\u2013402","DOI":"10.1007\/978-3-319-71667-1_20"},{"issue":"1","key":"606_CR16","doi-asserted-by":"publisher","first-page":"309","DOI":"10.46586\/tches.v2024.i1.309-335","volume":"2024","author":"B Gigerl","year":"2024","unstructured":"Gigerl B, Klug F, Mangard S et al (2024) Smooth passage with the guards: second-order hardware masking of the AES with low randomness and low latency. IACR Trans Cryptogr Hardw Embed Syst 2024(1):309\u2013335","journal-title":"IACR Trans Cryptogr Hardw Embed Syst"},{"key":"606_CR17","doi-asserted-by":"crossref","unstructured":"Gro\u00df H, Mangard S, Korak T (2016) Domain-oriented masking: compact masked hardware implementations with arbitrary protection order. In: Bilgin B, Nikova S, Rijmen V (eds) Proceedings of the ACM Workshop on Theory of Implementation Security, TIS@CCS 2016 Vienna, Austria, October, 2016. ACM, pp\u00a03","DOI":"10.1145\/2996366.2996426"},{"key":"#cr-split#-606_CR18.1","doi-asserted-by":"crossref","unstructured":"Gro\u00df H, Mangard S, Korak T (2017) An efficient side-channel protected AES implementation with arbitrary protection order. In: Handschuh H","DOI":"10.1007\/978-3-319-52153-4_6"},{"key":"#cr-split#-606_CR18.2","unstructured":"(ed) Topics in Cryptology - CT-RSA 2017 - The Cryptographers' Track at the RSA Conference 2017, San Francisco, CA, USA, February 14-17, 2017, Proceedings, Lecture Notes in Computer Science, vol 10159. Springer, pp 95-112"},{"issue":"2","key":"606_CR19","first-page":"1","volume":"2018","author":"H Gro\u00df","year":"2018","unstructured":"Gro\u00df H, Iusupov R, Bloem R (2018) Generic low-latency masking in hardware. IACR Trans Cryptogr Hardw Embed Syst 2018(2):1\u201321","journal-title":"IACR Trans Cryptogr Hardw Embed Syst"},{"key":"#cr-split#-606_CR20.1","doi-asserted-by":"crossref","unstructured":"Ishai Y, Sahai A, Wagner DA (2003) Private circuits: Securing hardware against probing attacks. In: Boneh D","DOI":"10.1007\/978-3-540-45146-4_27"},{"key":"#cr-split#-606_CR20.2","unstructured":"(ed) Advances in Cryptology - CRYPTO 2003, 23rd Annual International Cryptology Conference, Santa Barbara, California, USA, August 17-21, 2003, Proceedings, vol 2729. Lecture Notes in Computer Science. Springer, pp 463-481"},{"key":"606_CR21","doi-asserted-by":"crossref","unstructured":"Knichel D, Moradi A (2022) Low-latency hardware private circuits. In: Yin H, Stavrou A, Cremers C, et\u00a0al (eds) Proceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security, CCS 2022, Los Angeles, CA, USA, November 7-11, 2022. ACM, pp 1799\u20131812","DOI":"10.1145\/3548606.3559362"},{"key":"606_CR22","doi-asserted-by":"crossref","unstructured":"Knichel D, Sasdrich P, Moradi A (2020) SILVER - statistical independence and leakage verification. In: Moriai S, Wang H (eds) Advances in Cryptology - ASIACRYPT 2020 - 26th International Conference on the Theory and Application of Cryptology and Information Security, Daejeon, South Korea, December 7-11, 2020, Proceedings, Part I, Lecture Notes in Computer Science, vol 12491. Springer, pp 787\u2013816","DOI":"10.1007\/978-3-030-64837-4_26"},{"issue":"1","key":"606_CR23","first-page":"323","volume":"2022","author":"D Knichel","year":"2022","unstructured":"Knichel D, Sasdrich P, Moradi A (2022) Generic hardware private circuits towards automated generation of composable secure gadgets. IACR Trans Cryptogr Hardw Embed Syst 2022(1):323\u2013344","journal-title":"IACR Trans Cryptogr Hardw Embed Syst"},{"key":"#cr-split#-606_CR24.1","doi-asserted-by":"crossref","unstructured":"Kocher PC (1996) Timing attacks on implementations of diffie-hellman, rsa, dss, and other systems. In: Koblitz N","DOI":"10.1007\/3-540-68697-5_9"},{"key":"#cr-split#-606_CR24.2","unstructured":"(ed) Advances in Cryptology - CRYPTO '96, 16th Annual International Cryptology Conference, Santa Barbara, California, USA, August 18-22, 1996, Proceedings, Lecture Notes in Computer Science, vol 1109. Springer, pp 104-113"},{"key":"#cr-split#-606_CR25.1","doi-asserted-by":"crossref","unstructured":"Kocher PC, Jaffe J, Jun B (1999) Differential power analysis. In: Wiener MJ","DOI":"10.1007\/3-540-48405-1_25"},{"key":"#cr-split#-606_CR25.2","unstructured":"(ed) Advances in Cryptology - CRYPTO '99, 19th Annual International Cryptology Conference, Santa Barbara, California, USA, August 15-19, 1999, Proceedings, Lecture Notes in Computer Science, vol 1666. Springer, pp 388-397"},{"key":"606_CR26","unstructured":"Lammers D, M\u00fcller N, Moradi A (2023) Glitch-free is not enough - revisiting glitch-extended probing model. IACR Cryptol ePrint Arch pp 35"},{"key":"606_CR27","doi-asserted-by":"crossref","unstructured":"Mangard S, Popp T, Gammel BM (2005a) Side-channel leakage of masked CMOS gates. In: Menezes A (ed) Topics in Cryptology - CT-RSA 2005, The Cryptographers\u2019 Track at the RSA Conference 2005, San Francisco, CA, USA, February 14-18, 2005, Proceedings, Lecture Notes in Computer Science, vol 3376. Springer, pp 351\u2013365","DOI":"10.1007\/978-3-540-30574-3_24"},{"key":"606_CR28","doi-asserted-by":"crossref","unstructured":"Mangard S, Pramstaller N, Oswald E (2005b) Successfully attacking masked AES hardware implementations. In: Rao JR, Sunar B (eds) Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings, Lecture Notes in Computer Science, vol 3659. Springer, pp 157\u2013171","DOI":"10.1007\/11545262_12"},{"issue":"3","key":"606_CR29","doi-asserted-by":"publisher","first-page":"431","DOI":"10.46586\/tches.v2018.i3.431-468","volume":"2018","author":"LD Meyer","year":"2018","unstructured":"Meyer LD, Reparaz O, Bilgin B (2018) Multiplicative masking for AES in hardware. IACR Trans Cryptogr Hardw Embed Syst 2018(3):431\u2013468","journal-title":"IACR Trans Cryptogr Hardw Embed Syst"},{"issue":"2","key":"606_CR30","doi-asserted-by":"publisher","first-page":"256","DOI":"10.46586\/tches.v2019.i2.256-292","volume":"2019","author":"T Moos","year":"2019","unstructured":"Moos T, Moradi A, Schneider T et al (2019) Glitch-resistant masking revisited or why proofs in the robust probing model are needed. IACR Trans Cryptogr Hardw Embed Syst 2019(2):256\u2013292","journal-title":"IACR Trans Cryptogr Hardw Embed Syst"},{"key":"606_CR31","doi-asserted-by":"crossref","unstructured":"Moradi A, Schneider T (2016) Side-channel analysis protection and low-latency in action - - case study of PRINCE and midori -. In: Cheon JH, Takagi T (eds) Advances in Cryptology - ASIACRYPT 2016 - 22nd International Conference on the Theory and Application of Cryptology and Information Security, Hanoi, Vietnam, December 4-8, 2016, Proceedings, Part I, pp 517\u2013547","DOI":"10.1007\/978-3-662-53887-6_19"},{"issue":"4","key":"606_CR32","doi-asserted-by":"publisher","first-page":"693","DOI":"10.46586\/tches.v2022.i4.693-717","volume":"2022","author":"R Nagpal","year":"2022","unstructured":"Nagpal R, Gigerl B, Primas R et al (2022) Riding the waves towards generic single-cycle masking in hardware. IACR Trans Cryptogr Hardw Embed Syst 2022(4):693\u2013717","journal-title":"IACR Trans Cryptogr Hardw Embed Syst"},{"key":"606_CR33","doi-asserted-by":"crossref","unstructured":"Nikova S, Rechberger C, Rijmen V (2006) Threshold implementations against side-channel attacks and glitches. In: Ning P, Qing S, Li N (eds) Information and Communications Security, 8th International Conference, ICICS 2006, Raleigh, NC, USA, December 4-7, 2006, Proceedings, Lecture Notes in Computer Science, vol 4307. Springer, pp 529\u2013545","DOI":"10.1007\/11935308_38"},{"key":"606_CR34","doi-asserted-by":"crossref","unstructured":"Paar C, Pelzl J (2015) The advanced encryption standard (aes). In: Understanding Cryptography: A Textbook for Students and Practitioners. Springer, pp 87\u2013121","DOI":"10.1007\/978-3-642-04101-3_4"},{"issue":"2","key":"606_CR35","doi-asserted-by":"publisher","first-page":"300","DOI":"10.46586\/tches.v2020.i2.300-326","volume":"2020","author":"P Sasdrich","year":"2020","unstructured":"Sasdrich P, Bilgin B, Hutter M et al (2020) Low-latency hardware masking with application to AES. IACR Trans Cryptogr Hardw Embed Syst 2020(2):300\u2013326","journal-title":"IACR Trans Cryptogr Hardw Embed Syst"},{"key":"606_CR36","doi-asserted-by":"crossref","unstructured":"Simoes M, Bossuet L, Bruneau N, et\u00a0al (2022) Self-timed masking: Implementing masked s-boxes without registers. In: Buhan I, Schneider T (eds) Smart Card Research and Advanced Applications - 21st International Conference, CARDIS 2022, Birmingham, UK, November 7-9, 2022, Revised Selected Papers, Lecture Notes in Computer Science, vol 13820. Springer, pp 146\u2013164","DOI":"10.1007\/978-3-031-25319-5_8"},{"issue":"2","key":"606_CR37","doi-asserted-by":"publisher","first-page":"293","DOI":"10.46586\/tches.v2025.i2.293-332","volume":"2025","author":"Q Tian","year":"2025","unstructured":"Tian Q, Cheng H, Guo C et al (2025) A code-based ISE to protect boolean masking in software. IACR Trans Cryptogr Hardw Embed Syst 2025(2):293\u2013332","journal-title":"IACR Trans Cryptogr Hardw Embed Syst"},{"key":"606_CR38","doi-asserted-by":"crossref","unstructured":"Zhang Z, Petkova-Nikova S, Nikov V (2024) Glitch-stopping circuits: hardware secure masking without registers. In: Luo B, Liao X, Xu J, et\u00a0al (eds) Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security, CCS 2024, Salt Lake City, UT, USA, October 14-18, 2024. ACM, pp 3406\u20133420","DOI":"10.1145\/3658644.3670335"}],"container-title":["Cybersecurity"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1186\/s42400-026-00606-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1186\/s42400-026-00606-2","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1186\/s42400-026-00606-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,5,29]],"date-time":"2026-05-29T04:09:49Z","timestamp":1780027789000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1186\/s42400-026-00606-2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,5,29]]},"references-count":43,"journal-issue":{"issue":"1","published-online":{"date-parts":[[2026,12]]}},"alternative-id":["606"],"URL":"https:\/\/doi.org\/10.1186\/s42400-026-00606-2","relation":{},"ISSN":["2523-3246"],"issn-type":[{"value":"2523-3246","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,5,29]]},"assertion":[{"value":"24 November 2025","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"13 May 2026","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"29 May 2026","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors declare that they have no competing interests.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Competing Interests"}}],"article-number":"176"}}