{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,31]],"date-time":"2024-10-31T04:26:20Z","timestamp":1730348780623,"version":"3.28.0"},"reference-count":14,"publisher":"Science China Press., Co. Ltd.","issue":"6","license":[{"start":{"date-parts":[[2002,12,1]],"date-time":"2002-12-01T00:00:00Z","timestamp":1038700800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2002,12,1]],"date-time":"2002-12-01T00:00:00Z","timestamp":1038700800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sci China Ser F"],"published-print":{"date-parts":[[2002,12]]},"DOI":"10.1360\/02yf9040","type":"journal-article","created":{"date-parts":[[2023,10,9]],"date-time":"2023-10-09T17:43:01Z","timestamp":1696873381000},"page":"462-478","source":"Crossref","is-referenced-by-count":3,"title":["Clustering of behavioral phases in FSMs and its applications to VLSI test"],"prefix":"10.1360","volume":"45","author":[{"given":"Huawei","family":"Li","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yinghua","family":"Min","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhongcheng","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"294","reference":[{"key":"456462_CR1","volume-title":"Logic Design Principles","author":"E. J. McCluskey","year":"1986","unstructured":"McCluskey, E. J., Logic Design Principles, New Jersey: Prentice Hall, Englewood Cliffs: A Division of Simon & Schuster, Inc., 1986."},{"issue":"12","key":"456462_CR2","doi-asserted-by":"publisher","first-page":"1780","DOI":"10.1109\/43.811327","volume":"18","author":"K. L. Einspahr","year":"1999","unstructured":"Einspahr, K. L., Mehta, S. K., Seth, S. C., A synthesis for testability scheme for finite state machines using clock control, IEEE Transactions on Computer-Aided Design, 1999, 18(12): 1780\u20131792.","journal-title":"IEEE Transactions on Computer-Aided Design"},{"key":"456462_CR3","doi-asserted-by":"publisher","first-page":"214","DOI":"10.1109\/EDAC.1991.206393","volume-title":"Proc. of European Design Automation Conf.","author":"T. M. Niermann","year":"1991","unstructured":"Niermann, T. M., Patel, J. H., HITEC: A test generation package for sequential circuits, Proc. of European Design Automation Conf., Amsterdam: IEEE Computer Society Press, 1991, 214\u2013218."},{"key":"456462_CR4","first-page":"52","volume-title":"Proc. of 21st Fault-Tolerant Computing Symposium","author":"I. Pomeranz","year":"1991","unstructured":"Pomeranz, I., Reddy, S. M., Test generation for synchronous sequential circuits using multiple observation times, Proc. of 21st Fault-Tolerant Computing Symposium, Montreal: IEEE Computer Society Press, 1991, 52\u201359."},{"issue":"9","key":"456462_CR5","first-page":"1104","volume":"37","author":"Z. Li","year":"1994","unstructured":"Li, Z., Pan, Y., Min, Y., SABATPG: A structural analysis based automatic test pattern generation system, Science in China (Series A), 1994, 37(9): 1104\u20131114.","journal-title":"Science in China (Series A)"},{"issue":"6","key":"456462_CR6","doi-asserted-by":"publisher","first-page":"1015","DOI":"10.1109\/43.238038","volume":"17","author":"S. T. Chakradhar","year":"1993","unstructured":"Chakradhar, S. T., Agrawal, V. D., Rothweiler, S. G., A transitive closure algorithm for test generation, IEEE Transactions on Computer-Aided Design, 1993, 17(6): 1015\u20131028.","journal-title":"IEEE Transactions on Computer-Aided Design"},{"issue":"2","key":"456462_CR7","doi-asserted-by":"publisher","first-page":"63","DOI":"10.1023\/A:1008355411566","volume":"15","author":"I. Hamzaoglu","year":"1999","unstructured":"Hamzaoglu, I., Patel, J. H., New techniques for deterministic test generation, Journal of Electronic Testing: Theory and Applications, 1999, 15(2): 63\u201373.","journal-title":"Journal of Electronic Testing: Theory and Applications"},{"key":"456462_CR8","first-page":"272","volume-title":"Proc. of European Design and Test Conf.","author":"S. Bhatia","year":"1994","unstructured":"Bhatia, S., Jha, N. K., Genesis: A behavioral synthesis system for hierarchical testability, Proc. of European Design and Test Conf., Paris: IEEE Computer Society Press, 1994, 272\u2013276."},{"issue":"8","key":"456462_CR9","doi-asserted-by":"publisher","first-page":"706","DOI":"10.1109\/43.712102","volume":"17","author":"I. Ghosh","year":"1998","unstructured":"Ghosh, I., Raghunathan, A., Jha, N. K., A DFT technique for RTL circuits using control\/data flow extraction, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998, 17(8): 706\u2013723.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"2","key":"456462_CR10","doi-asserted-by":"publisher","first-page":"105","DOI":"10.1023\/A:1008301720070","volume":"13","author":"Y. Makris","year":"1998","unstructured":"Makris, Y., Orailoglu, A., RTL Test justification and propagation analysis for modular designs, Journal of Electronic Testing: Theory & Applications, 1998, 13(2): 105\u2013120.","journal-title":"Journal of Electronic Testing: Theory & Applications"},{"key":"456462_CR11","doi-asserted-by":"publisher","first-page":"185","DOI":"10.1109\/ATS.2000.893623","volume-title":"Proc. of Asian Test Symp.","author":"Y. Makris","year":"2000","unstructured":"Makris, Y., Collins, J., Orailog\u011flu, A., Fast hierarchical test path construction for DFT-free controller-datapath circuits, Proc. of Asian Test Symp., Taipei: IEEE Computer Society Press, 2000, 185\u2013190."},{"key":"456462_CR12","first-page":"44","volume-title":"IEEE Design & Test of Computers","author":"F. Corno","year":"2000","unstructured":"Corno, F., Reorda, M. S., Squillero, G., RT-level ITC\u201999 benchmarks and first ATPG results, IEEE Design & Test of Computers, Montreal: IEEE Computer Society Press, 2000, 17(3): 44\u201353."},{"key":"456462_CR13","doi-asserted-by":"crossref","unstructured":"Corno, F., Reorda, M. S., Squillero, G., High-level observability for effective high-level ATPG, Proc. of 18th IEEE VLSI Test Symposium, 2000, 411\u2013416.","DOI":"10.1109\/VTEST.2000.843872"},{"key":"456462_CR14","volume-title":"VHDL for Designers","author":"S. Sjoholm","year":"1997","unstructured":"Sjoholm, S., Lindh, L., VHDL for Designers, New Jersey: Prentice Hall, Inc. A Simon & Schuster Company, 1997."}],"container-title":["Science in China Series F Information Sciences"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1360\/02yf9040.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1360\/02yf9040\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1360\/02yf9040.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T12:46:29Z","timestamp":1730292389000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1360\/02yf9040"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,12]]},"references-count":14,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2002,12]]}},"alternative-id":["456462"],"URL":"https:\/\/doi.org\/10.1360\/02yf9040","relation":{},"ISSN":["1009-2757","1862-2836"],"issn-type":[{"type":"print","value":"1009-2757"},{"type":"electronic","value":"1862-2836"}],"subject":[],"published":{"date-parts":[[2002,12]]}}}