{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,14]],"date-time":"2025-05-14T04:17:00Z","timestamp":1747196220988,"version":"3.40.5"},"reference-count":34,"publisher":"Public Library of Science (PLoS)","issue":"2","license":[{"start":{"date-parts":[[2022,2,22]],"date-time":"2022-02-22T00:00:00Z","timestamp":1645488000000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["www.plosone.org"],"crossmark-restriction":false},"short-container-title":["PLoS ONE"],"abstract":"<jats:p>Low-power consumption has been always a crucial design constraint for an efficient intellectual property based three-dimensional multi-core system that cannot be ignored easily. As the complexity increases due to the number of cores\/stacks\/ layers in 3D digital systems, the challenges to handle power can be more difficult at a high abstraction level. Therefore, the low-power approach gives designers an opportunity to estimate and optimize the power consumption in the early stages of design phases. The accurate power estimation through the macro-modeling approach at high-level reduces the risk of redesign cycle and turn-around time. In this research, we have presented an improved statistical macro-modeling approach that estimates power through statistical characteristics of randomly generated input patterns by using Biogeography Based Optimization. These input patterns propagate signals into an IP-based 3D digital test system. In experiments, the test system is based on four 8 to 32- bits heterogeneous cores. The response of the power is monitored by applying the well-known Monte Carlo Simulation technique. The entire power estimation method is performed in two major steps. First, the average power is estimated for an IP-based individual core. Second, the average power for bus-based Through-Silicon-Via is estimated. Finally, the cores and B-TSVs are integrated together to construct a 3D system. Then the average power for complete test systems is estimated. The experimental results of the statistical power macro-model are compared with the commercial Electronic Design Automation power simulator at the operating frequency of 100 MHz. The average percentage error of the test system is calculated as 8.65%. For the validation of these results, the statistical error analysis is additionally performed and reveals that our proposed macro-model is accurate in terms of percentage of error with a feasible amount of time.<\/jats:p>","DOI":"10.1371\/journal.pone.0264181","type":"journal-article","created":{"date-parts":[[2022,2,22]],"date-time":"2022-02-22T18:29:07Z","timestamp":1645554547000},"page":"e0264181","update-policy":"https:\/\/doi.org\/10.1371\/journal.pone.corrections_policy","source":"Crossref","is-referenced-by-count":0,"title":["Efficient power macromodeling approach for heterogeneously stacked 3d ICs using Bio-geography based optimization"],"prefix":"10.1371","volume":"17","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1998-5351","authenticated-orcid":true,"given":"Faisal","family":"Siddiq","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yaseer Arafat","family":"Durrani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"340","published-online":{"date-parts":[[2022,2,22]]},"reference":[{"issue":"4","key":"pone.0264181.ref001","doi-asserted-by":"crossref","first-page":"435","DOI":"10.1166\/jolpe.2013.1283","article-title":"High-Level Power Analysis for Ip-Based Digital Systems","volume":"9","author":"YA Durrani","year":"2013","journal-title":"ASP Journal of Low Power Electronics"},{"key":"pone.0264181.ref002","doi-asserted-by":"crossref","unstructured":"Butts JA, Sohi GS. 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