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To solve this problem, in this paper we present a hardware-based complex event detection system implemented on\n            <jats:italic>field-programmable gate arrays<\/jats:italic>\n            (FPGAs). By inserting the FPGA directly into the data path between the network interface and the CPU, our solution can detect complex events at gigabit wire speed with constant and fully predictable latency, independently of network load, packet size, or data distribution. This is a significant improvement over CPU-based systems and an architectural approach that opens up interesting opportunities for hybrid stream engines that combine the flexibility of the CPU with the parallelism and processing power of FPGAs.\n          <\/jats:p>","DOI":"10.14778\/1920841.1920926","type":"journal-article","created":{"date-parts":[[2014,6,24]],"date-time":"2014-06-24T12:17:57Z","timestamp":1403612277000},"page":"660-669","source":"Crossref","is-referenced-by-count":59,"title":["Complex event detection at wire speed with FPGAs"],"prefix":"10.14778","volume":"3","author":[{"given":"Louis","family":"Woods","sequence":"first","affiliation":[{"name":"ETH Zurich, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jens","family":"Teubner","sequence":"additional","affiliation":[{"name":"ETH Zurich, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gustavo","family":"Alonso","sequence":"additional","affiliation":[{"name":"ETH Zurich, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,9]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1376616.1376634"},{"key":"e_1_2_1_2_1","volume-title":"Scalable Pattern Matching for High Speed Networks. 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