{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,14]],"date-time":"2026-03-14T09:52:38Z","timestamp":1773481958915,"version":"3.50.1"},"reference-count":21,"publisher":"Association for Computing Machinery (ACM)","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Proc. VLDB Endow."],"published-print":{"date-parts":[[2019,8]]},"abstract":"<jats:p>Currently, we face the next major shift in processor designs that arose from the physical limitations known as the \"dark silicon effect\". Due to thermal limitations and shrinking transistor sizes, multi-core scaling is coming to an end. A major new direction that hardware vendors are currently investigating involves specialized and energy-efficient hardware accelerators (e.g., ASICs) placed on the same die as the normal CPU cores.<\/jats:p>\n          <jats:p>\n            In this paper, we present a novel query processing engine called\n            <jats:italic>SiliconDB<\/jats:italic>\n            that targets such heterogeneous processor environments. We leverage the Sparc M7 platform to develop and test our ideas. Based on the SSB benchmarks, as well as other micro benchmarks, we compare the efficiency of\n            <jats:italic>SiliconDB<\/jats:italic>\n            with existing execution strategies that make use of co-processors (e.g., FPGAs, GPUs) and demonstrate speed-up improvements of up to 2x.\n          <\/jats:p>","DOI":"10.14778\/3352063.3352137","type":"journal-article","created":{"date-parts":[[2019,9,18]],"date-time":"2019-09-18T18:36:11Z","timestamp":1568831771000},"page":"2218-2229","source":"Crossref","is-referenced-by-count":10,"title":["A morsel-driven query execution engine for heterogeneous multi-cores"],"prefix":"10.14778","volume":"12","author":[{"given":"Kayhan","family":"Dursun","sequence":"first","affiliation":[{"name":"Brown University"}]},{"given":"Carsten","family":"Binnig","sequence":"additional","affiliation":[{"name":"TU Darmstadt"}]},{"given":"Ugur","family":"Cetintemel","sequence":"additional","affiliation":[{"name":"Brown University"}]},{"given":"Garret","family":"Swart","sequence":"additional","affiliation":[{"name":"Oracle Corporation"}]},{"given":"Weiwei","family":"Gong","sequence":"additional","affiliation":[{"name":"Oracle Corporation"}]}],"member":"320","published-online":{"date-parts":[[2019,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.14778\/2336664.2336678"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.14778\/2732219.2732227"},{"key":"e_1_2_1_3_1","volume-title":"Datenbank-Spektrum","author":"Bre\u00df S.","year":"2014","unstructured":"S. Bre\u00df . The design and implementation of cogadb: A column-oriented gpu-accelerated DBMS . Datenbank-Spektrum , 2014 . S. Bre\u00df. The design and implementation of cogadb: A column-oriented gpu-accelerated DBMS. Datenbank-Spektrum, 2014."},{"key":"e_1_2_1_4_1","volume-title":"ADBIS","author":"Bre\u00df S.","year":"2012","unstructured":"S. Bre\u00df Automatic selection of processing units for coprocessing in databases . In ADBIS , 2012 . S. Bre\u00df et al. Automatic selection of processing units for coprocessing in databases. In ADBIS, 2012."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2882903.2882936"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.14778\/2733004.2733042"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/3183713.3183734"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.77"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1066157.1066201"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.14778\/2536206.2536216"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.14778\/2735496.2735497"},{"key":"e_1_2_1_12_1","first-page":"1","article-title":"Sparc m7: A 20 nm 32-core 64 mb l3 cache processor","volume":"51","author":"Konstadinidis G.","year":"2015","unstructured":"G. Konstadinidis Sparc m7: A 20 nm 32-core 64 mb l3 cache processor . IEEE Journal of Solid-State Circuits , 51 : 1 -- 13 , 2015 . G. Konstadinidis et al. Sparc m7: A 20 nm 32-core 64 mb l3 cache processor. IEEE Journal of Solid-State Circuits, 51:1--13, 2015.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2588555.2610507"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.14778\/1687627.1687730"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.14778\/1687627.1687654"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.14778\/2002938.2002940"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2011.4"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2771937.2771941"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.14778\/3015274.3015275"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.5555\/3014904.3015005"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICDE.2017.120"}],"container-title":["Proceedings of the VLDB Endowment"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.14778\/3352063.3352137","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,28]],"date-time":"2022-12-28T10:34:31Z","timestamp":1672223671000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.14778\/3352063.3352137"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,8]]},"references-count":21,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2019,8]]}},"alternative-id":["10.14778\/3352063.3352137"],"URL":"https:\/\/doi.org\/10.14778\/3352063.3352137","relation":{},"ISSN":["2150-8097"],"issn-type":[{"value":"2150-8097","type":"print"}],"subject":[],"published":{"date-parts":[[2019,8]]}}}