{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,11]],"date-time":"2025-11-11T13:58:47Z","timestamp":1762869527367,"version":"3.38.0"},"reference-count":12,"publisher":"Walter de Gruyter GmbH","issue":"4-5","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,8,26]]},"abstract":"<jats:title>Abstract<\/jats:title>\n               <jats:p xml:lang=\"en\">This paper proposes two approaches to design of arithmetic units. The first approach considers the result of calculations as the system of the positive polarity Reed-Muller expansions. The second approach decomposes arithmetic operations into a set of up to 5-input Boolean functions. Standard multipliers, multipliers by modulo, and composite operations in small-bit ranges are considered. An expression for the calculation of the most significant bit of modular multiplication is represented.<\/jats:p>","DOI":"10.1515\/itit-2024-0070","type":"journal-article","created":{"date-parts":[[2025,2,26]],"date-time":"2025-02-26T14:09:49Z","timestamp":1740578989000},"page":"114-123","source":"Crossref","is-referenced-by-count":1,"title":["Two approaches of arithmetic units design"],"prefix":"10.1515","volume":"66","author":[{"given":"Danila","family":"Gorodecky","sequence":"first","affiliation":[{"name":"INESC-ID, Instituto Superior Tecnico , Universidade de Lisboa , Lisbon , Portugal"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"374","published-online":{"date-parts":[[2025,2,26]]},"reference":[{"key":"2025030616183073843_j_itit-2024-0070_ref_001","unstructured":"D. Harris and S. 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Fujita, Representations of Discrete Functions, New York, USA, Kluwer, 1996.","DOI":"10.1007\/978-1-4613-1385-4"},{"key":"2025030616183073843_j_itit-2024-0070_ref_006","doi-asserted-by":"crossref","unstructured":"C. Carlet, Boolean Functions for Cryptography and Coding Theory, UK, Cambridge Univ. Press, 2021.","DOI":"10.1017\/9781108606806"},{"key":"2025030616183073843_j_itit-2024-0070_ref_007","doi-asserted-by":"crossref","unstructured":"A. Bottcher and M. Kumm, \u201cSmall logic-based multipliers with incomplete sub-multipliers for FPGAs,\u201d in Proceedings of the 31th IEEE Symposium on Computer Arithmetic, June 10\u201312, 2024, Malaga, Spain, 2024.","DOI":"10.1109\/ARITH61463.2024.00029"},{"key":"2025030616183073843_j_itit-2024-0070_ref_008","unstructured":"D. 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