{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T15:00:18Z","timestamp":1773414018091,"version":"3.50.1"},"reference-count":26,"publisher":"Walter de Gruyter GmbH","issue":"4-5","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,8,26]]},"abstract":"<jats:title>Abstract<\/jats:title>\n               <jats:p xml:lang=\"en\">Approximate computing is an fast developing area for resource-efficient and fast designs that trades off computational accuracy with non-functional aspects such as delay, energy requirements or area. It can be used for applications where it is acceptable to compute inaccurate results such as image processing. A lot of work has been published on approximate synthesis for ASICs. As FPGAs are becoming more prevalent, approximation techniques for this technology should be developed. Lookup tables are a scarce resource on FPGAs. Consequently, we present and evaluate multiple approaches for reducing the number of lookup tables required to implement a given design on an FPGA. Our approaches work by removing either wires or entire lookup tables from a lookup table network. We can show that our approach is faster than related work while removing a comparable number of lookup tables (more in most cases).<\/jats:p>","DOI":"10.1515\/itit-2024-0074","type":"journal-article","created":{"date-parts":[[2025,2,14]],"date-time":"2025-02-14T10:21:00Z","timestamp":1739528460000},"page":"137-146","source":"Crossref","is-referenced-by-count":1,"title":["Approximate synthesis for LUT count reduction via probabilistic error propagation"],"prefix":"10.1515","volume":"66","author":[{"given":"Thomas","family":"Schl\u00f6gl","sequence":"first","affiliation":[{"name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU) , Erlangen , Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oliver","family":"Keszocze","sequence":"additional","affiliation":[{"name":"Technical University of Denmark , Lyngby , Denmark"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"374","published-online":{"date-parts":[[2025,2,17]]},"reference":[{"key":"2025030616183064914_j_itit-2024-0074_ref_001","doi-asserted-by":"crossref","unstructured":"J. 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Keszocze, \u201cBDD-based error metric analysis, computation and optimization,\u201d IEEE Access, vol.\u00a010, pp.\u00a014013\u201314028, 2022. https:\/\/doi.org\/10.1109\/access.2022.3140557.","DOI":"10.1109\/ACCESS.2022.3140557"},{"key":"2025030616183064914_j_itit-2024-0074_ref_005","doi-asserted-by":"crossref","unstructured":"M. Shafique, et al.., \u201cA low latency generic accuracy configurable adder,\u201d in Design Automation Conference, 2015.","DOI":"10.1145\/2744769.2744778"},{"key":"2025030616183064914_j_itit-2024-0074_ref_006","unstructured":"H. Jiang, et al.., \u201cA comparative evaluation of approximate multipliers,\u201d in International Symposium on Nanoscale Architectures, 2016."},{"key":"2025030616183064914_j_itit-2024-0074_ref_007","doi-asserted-by":"crossref","unstructured":"V. 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IEEE, vol.\u00a0108, no.\u00a012, pp.\u00a02103\u20132107, 2020. https:\/\/doi.org\/10.1109\/jproc.2020.3033361.","DOI":"10.1109\/JPROC.2020.3033361"},{"key":"2025030616183064914_j_itit-2024-0074_ref_011","doi-asserted-by":"crossref","unstructured":"J. Echavarria, et al.., \u201cCan approximate computing reduce power consumption on FPGAs?\u201d in International Conference on Electronics, Circuits and Systems, 2018.","DOI":"10.1109\/ICECS.2018.8618062"},{"key":"2025030616183064914_j_itit-2024-0074_ref_012","doi-asserted-by":"crossref","unstructured":"J. Echavarria, et al.., \u201cFAU: fast and error-optimized approximate adder units on LUT-based FPGAs,\u201d in International Conference on Field-Programmable Technology, 2016.","DOI":"10.1109\/FPT.2016.7929536"},{"key":"2025030616183064914_j_itit-2024-0074_ref_013","doi-asserted-by":"crossref","unstructured":"J. Cong and Y. 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Soeken, et al.., \u201cThe EPFL logic synthesis libraries,\u201d arXiv preprint arXiv:1805.05121, 2019. https:\/\/doi.org\/10.48550\/arXiv.1805.05121."}],"container-title":["it - Information Technology"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.degruyter.com\/document\/doi\/10.1515\/itit-2024-0074\/xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/www.degruyter.com\/document\/doi\/10.1515\/itit-2024-0074\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,6]],"date-time":"2025-03-06T16:18:49Z","timestamp":1741277929000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.degruyter.com\/document\/doi\/10.1515\/itit-2024-0074\/html"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,8,1]]},"references-count":26,"journal-issue":{"issue":"4-5","published-online":{"date-parts":[[2025,3,3]]},"published-print":{"date-parts":[[2024,8,26]]}},"alternative-id":["10.1515\/itit-2024-0074"],"URL":"https:\/\/doi.org\/10.1515\/itit-2024-0074","relation":{},"ISSN":["1611-2776","2196-7032"],"issn-type":[{"value":"1611-2776","type":"print"},{"value":"2196-7032","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,8,1]]}}}