{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,7]],"date-time":"2025-03-07T05:18:37Z","timestamp":1741324717857,"version":"3.38.0"},"reference-count":20,"publisher":"Walter de Gruyter GmbH","issue":"4-5","funder":[{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"crossref","award":["471837173"],"award-info":[{"award-number":["471837173"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,8,26]]},"abstract":"<jats:title>Abstract<\/jats:title>\n               <jats:p xml:lang=\"en\">A significant challenge hindering the widespread adoption of approximate hardware units is the complexity associated with test and error evaluation. We address this issue by extending Information Flow Tracking (IFT) for hardware designs to accommodate approximate units. Unlike conventional IFT approaches, our system employs a dynamic, error-responsive tag-based mechanism that facilitates tracking the error characteristics and their propagation within approximate units. Such an approach is vital in the domain of approximate computing, where uncommon yet substantial errors, such as those found in Equal Segmentation Adders (ESA), can markedly influence computation accuracy and reliability. By focusing on the dynamic nature of errors and their traceability, our methodology supports understanding the effects of approximation errors, thereby promoting their broader utilisation in various applications. The results of our study demonstrate the potential of analysing error propagation in approximate designs.<\/jats:p>","DOI":"10.1515\/itit-2024-0075","type":"journal-article","created":{"date-parts":[[2024,12,13]],"date-time":"2024-12-13T08:55:53Z","timestamp":1734080153000},"page":"147-158","source":"Crossref","is-referenced-by-count":0,"title":["Detailed insight into approximate circuits with error-responsive information flow tracking"],"prefix":"10.1515","volume":"66","author":[{"given":"Lutz","family":"Schammer","sequence":"first","affiliation":[{"name":"Hamburg University of Technology , Hamburg , Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gianluca","family":"Martino","sequence":"additional","affiliation":[{"name":"Hamburg University of Technology , Hamburg , Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amir","family":"Najafi","sequence":"additional","affiliation":[{"name":"University of Bremen , Bremen , Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alberto","family":"Garcia-Ortiz","sequence":"additional","affiliation":[{"name":"University of Bremen , Bremen , Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Goerschwin","family":"Fey","sequence":"additional","affiliation":[{"name":"Hamburg University of Technology , Hamburg , Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"374","published-online":{"date-parts":[[2024,12,13]]},"reference":[{"key":"2025030616183069253_j_itit-2024-0075_ref_001","doi-asserted-by":"crossref","unstructured":"A. Najafi, M. Wei\u00dfbrich, G. Pay\u00e1-Vay\u00e1, and A. Garcia-Ortiz, \u201cCoherent design of hybrid approximate adders: unified design framework and metrics,\u201d IEEE J. Emerg. Sel. Top. Circuits Syst., vol.\u00a08, no.\u00a04, pp.\u00a0736\u2013745, 2018. https:\/\/doi.org\/10.1109\/JETCAS.2018.2833284.","DOI":"10.1109\/JETCAS.2018.2833284"},{"key":"2025030616183069253_j_itit-2024-0075_ref_002","doi-asserted-by":"crossref","unstructured":"M. Ceska, J. Maty\u00e1s, V. Mrazek, L. Sekanina, Z. Vas\u00edcek, and T. Vojnar, \u201cApproximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished,\u201d in 2017 IEEE\/ACM International Conference on Computer-Aided Design, ICCAD 2017, Irvine, CA, USA, November 13-16, 2017, S. Parameswaran, Ed., IEEE, 2017, pp.\u00a0416\u2013423.","DOI":"10.1109\/ICCAD.2017.8203807"},{"key":"2025030616183069253_j_itit-2024-0075_ref_003","doi-asserted-by":"crossref","unstructured":"W. Hu, A. Ardeshiricham, and R. Kastner, \u201cHardware information flow tracking,\u201d ACM Comput. Surv., vol.\u00a054, no.\u00a04, pp.\u00a01\u201339, 2021. https:\/\/doi.org\/10.1145\/3447867.","DOI":"10.1145\/3447867"},{"key":"2025030616183069253_j_itit-2024-0075_ref_004","doi-asserted-by":"crossref","unstructured":"M. Hao, A. Najafi, A. Garc\u00eda-Ortiz, L. Karsthof, S. Paul, and J. Rust, \u201cReliability of an industrial wireless communication system using approximate units,\u201d in 2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2019, pp.\u00a087\u201390.","DOI":"10.1109\/PATMOS.2019.8862161"},{"key":"2025030616183069253_j_itit-2024-0075_ref_005","doi-asserted-by":"crossref","unstructured":"S. Froehlich, D. Gro\u00dfe, and R. Drechsler, \u201cOne method \u2013 all error-metrics: a three-stage approach for error-metric evaluation in approximate computing,\u201d in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, pp.\u00a0284\u2013287.","DOI":"10.23919\/DATE.2019.8715138"},{"key":"2025030616183069253_j_itit-2024-0075_ref_006","doi-asserted-by":"crossref","unstructured":"Z. Vasicek, \u201cFormal methods for exact analysis of approximate circuits,\u201d IEEE Access, vol.\u00a07, pp.\u00a0177309\u2013177331, 2019. https:\/\/doi.org\/10.1109\/ACCESS.2019.2958605.","DOI":"10.1109\/ACCESS.2019.2958605"},{"key":"2025030616183069253_j_itit-2024-0075_ref_007","doi-asserted-by":"crossref","unstructured":"M. Nadeem, C. K. Jha, and R. Drechsler, \u201cPolynomial formal verification of approximate adders with constant cutwidth,\u201d in IEEE European Test Symposium, ETS 2024, The Hague, Netherlands, May 20-24, 2024, IEEE, 2024, pp.\u00a01\u20136.","DOI":"10.1109\/ETS61313.2024.10567242"},{"key":"2025030616183069253_j_itit-2024-0075_ref_008","doi-asserted-by":"crossref","unstructured":"A. Ardeshiricham, W. Hu, J. Marxen, and R. Kastner, \u201cRegister transfer level information flow tracking for provably secure hardware design,\u201d in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, pp.\u00a01691\u20131696.","DOI":"10.23919\/DATE.2017.7927266"},{"key":"2025030616183069253_j_itit-2024-0075_ref_009","doi-asserted-by":"crossref","unstructured":"M. Hassan, V. Herdt, H. M. Le, D. Gro\u00dfe, and R. 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