{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T12:37:22Z","timestamp":1648989442112},"reference-count":10,"publisher":"Walter de Gruyter GmbH","issue":"4","license":[{"start":{"date-parts":[[2015,12,1]],"date-time":"2015-12-01T00:00:00Z","timestamp":1448928000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,12,1]]},"abstract":"<jats:title>Abstract<\/jats:title>\n\t\t\t\t<jats:p> The paper presents a second order current mode sigma-delta modulator designed with the help of a new elaborated tool to optimize the transistor sizes. The circuit is composed of two continuous time loop filters, a current comparator and a one bit DAC with a current output. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 250 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 53.6 dB while dissipating 93 \u03bcW, which corresponds to an efficiency of 59.7 fJ\/conv. The fully current mode structure makes the circuit suitable to be applied in a current mode signal processing like biosensors or image pixels arrays.<\/jats:p>","DOI":"10.1515\/bpasts-2015-0104","type":"journal-article","created":{"date-parts":[[2015,12,14]],"date-time":"2015-12-14T17:01:19Z","timestamp":1450112479000},"page":"919-922","source":"Crossref","is-referenced-by-count":6,"title":["Current mode sigma-delta modulator designed with the help of transistor\u2019s size optimization tool"],"prefix":"10.1515","volume":"63","author":[{"given":"P.","family":"\u015aniata\u0142a","sequence":"first","affiliation":[]},{"given":"M.","family":"Naumowicz","sequence":"additional","affiliation":[]},{"given":"A.","family":"Handkiewicz","sequence":"additional","affiliation":[]},{"given":"S.","family":"Szcz\u0119sny","sequence":"additional","affiliation":[]},{"given":"J.L.A. de","family":"Melo","sequence":"additional","affiliation":[]},{"given":"N.","family":"Paulino","sequence":"additional","affiliation":[]},{"given":"J.","family":"Goes","sequence":"additional","affiliation":[]}],"member":"374","reference":[{"key":"ref51","first-page":"157","article-title":"Low - power cmos continuous - time filters Solid - State Circuits","volume":"31","author":"Zele","year":"1996","journal-title":"IEEE"},{"key":"ref41","first-page":"39","article-title":"Low voltage integrators for high - frequency CMOS filters using current mode techniques Circuits and Systems - II : Analog and Digital Signal Processing","volume":"43","author":"Smith","year":"1996","journal-title":"IEEE Trans"},{"key":"ref31","doi-asserted-by":"crossref","first-page":"1747","DOI":"10.1109\/16.628832","article-title":"Pain On - focal - plane signal processing for current - mode active pixel sensors Devices","volume":"44","author":"Nakamura","year":"1997","journal-title":"IEEE Trans Electron"},{"key":"ref101","first-page":"2381","article-title":"- A fifth - order continuous - time \u0394\u03a3 modulator with process - insensitive input linear range Solid - State Circuits","volume":"44","author":"Aiba","year":"2009","journal-title":"IEEE"},{"key":"ref81","first-page":"326","article-title":"Automation of CMOS technology migration illustrated by RGB to YCrCb","volume":"21","author":"Naumowicz","year":"2013","journal-title":"Rev"},{"key":"ref11","first-page":"61","article-title":"Low power - bit pipelined and - bit self - calibrated A converters for a DSP system Pol","volume":"9","author":"Wawryn","year":"2013","journal-title":"Bull Tech"},{"key":"ref111","first-page":"330","article-title":"mW - MHz continuoustime \u0394\u03a3 modulator with a hybrid active - passive loop filter Solid - State Circuits","volume":"2","author":"Song","year":"2008","journal-title":"IEEE"},{"key":"ref71","doi-asserted-by":"crossref","first-page":"310","DOI":"10.1049\/el:19920192","article-title":"Novel approach to high speed CMOS current comparators","volume":"28","author":"Tr\u00e4ff","year":"1992","journal-title":"Electronics Letters"},{"key":"ref01","first-page":"61","article-title":"Rapid prototyping of algorithmic converters based on FPAA devices Pol","author":"Suszy\u0144ski","year":"2013","journal-title":"Bull Tech"},{"key":"ref61","doi-asserted-by":"crossref","first-page":"695","DOI":"10.1049\/el:19830474","article-title":"CMOS current comparator circuit","volume":"17","author":"Freitas","year":"1983","journal-title":"Electronics Letters"}],"container-title":["Bulletin of the Polish Academy of Sciences Technical Sciences"],"original-title":[],"link":[{"URL":"http:\/\/content.sciendo.com\/view\/journals\/bpasts\/63\/4\/article-p919.xml","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/www.degruyter.com\/view\/j\/bpasts.2015.63.issue-4\/bpasts-2015-0104\/bpasts-2015-0104.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,7,22]],"date-time":"2019-07-22T15:43:07Z","timestamp":1563810187000},"score":1,"resource":{"primary":{"URL":"http:\/\/journals.pan.pl\/dlibra\/publication\/97786\/edition\/84374\/content"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12,1]]},"references-count":10,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1515\/bpasts-2015-0104","relation":{},"ISSN":["2300-1917"],"issn-type":[{"value":"2300-1917","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,12,1]]}}}