{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,24]],"date-time":"2026-07-24T18:47:28Z","timestamp":1784918848248,"version":"3.55.0"},"reference-count":245,"publisher":"Emerald","issue":"2","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,4,18]]},"abstract":"<jats:p>Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device\u2019s speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the pro-grammability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.<\/jats:p>","DOI":"10.1561\/1000000005","type":"journal-article","created":{"date-parts":[[2008,5,4]],"date-time":"2008-05-04T02:59:11Z","timestamp":1209869951000},"page":"135-253","source":"Crossref","is-referenced-by-count":354,"title":["FPGA Architecture: Survey and Challenges"],"prefix":"10.1108","volume":"2","author":[{"given":"Ian","family":"Kuon","sequence":"first","affiliation":[{"name":"University of Toronto The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, , , ,","place":["Toronto, ON, Canada"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Russell","family":"Tessier","sequence":"additional","affiliation":[{"name":"University of Massachusetts Department of Electrical and Computer Engineering, , , ,","place":["Amherst, MA, USA"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jonathan","family":"Rose","sequence":"additional","affiliation":[{"name":"University of Toronto The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, , , ,","place":["Toronto, ON, Canada"]}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"140","published-online":{"date-parts":[[2008,4,18]]},"reference":[{"key":"2026032901121504800_ref001","unstructured":"Actel Corporation\n          , \u201cACT 1 series FPGAs,\u201d http:\/\/www.actel.com\/documents\/ACTl_DS.pdf, April1996."},{"key":"2026032901121504800_ref002","unstructured":"Actel Corporation\n          , \u201cAxcelerator family FPGAs,\u201d http:\/\/www.actel.com\/documents\/AX_DS.pdf, May2005."},{"key":"2026032901121504800_ref003","unstructured":"Actel Corporation\n          , \u201cProASIC3 flash family FPGAs,\u201d http:\/\/www.actel.com\/documents\/PA3JDS.pdf, October2005."},{"key":"2026032901121504800_ref004","unstructured":"Actel Corporation\n          , \u201cSingle-event effects in FPGAs,\u201d http:\/\/www.actel.com\/documents\/FirmErrorPIB.pdf, 2007."},{"key":"2026032901121504800_ref005","unstructured":"Actel Corporation\n          , \u201cSX-A family FPGAs v5.3,\u201d http:\/\/www.actel.com\/documents\/SXA-DS.pdf, February2007."},{"key":"2026032901121504800_ref006","first-page":"475","article-title":"Routing architectures for hierarchical field-programmable gate arrays","author":"Aggarwal"},{"key":"2026032901121504800_ref007","volume-title":"The Effect of Logic Block Granularity on Deep-Submicron FPGA Performance and Density","author":"Ahmed","year":"2001"},{"key":"2026032901121504800_ref008","first-page":"312","article-title":"The effect of LUT and cluster size on deep-submicron FPGA performance and density","author":"Ahmed","year":"2000"},{"issue":"3","key":"2026032901121504800_ref009","doi-asserted-by":"crossref","first-page":"288","DOI":"10.1109\/TVLSI.2004.824300","article-title":"The effect of LUT and cluster size on deep-submicron FPGA performance and density","volume":"12","author":"Ahmed","year":"2004","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"2026032901121504800_ref010","first-page":"115","article-title":"Single event effects test results for advanced field programmable gate arrays","author":"Allen","year":"2006"},{"key":"2026032901121504800_ref011","unstructured":"Altera Corporation\n          , \u201cClassic EPLD family data sheet. A-DS-CLASSIC-05,\u201d http:\/\/www.altera.com\/literature\/ds\/classic.pdf, May1999."},{"key":"2026032901121504800_ref012","unstructured":"Altera Corporation\n          , \u201cAPEX II programmable logic device family, DSAPEXII-3.0,\u201d http:\/\/www.altera.com\/literature\/ds\/ds_ap2.pdf, August2002."},{"key":"2026032901121504800_ref013","volume-title":"Excalibur device overview DS-EXCARM-2.0","author":"Altera Corporation","year":"2002"},{"key":"2026032901121504800_ref014","unstructured":"Altera Corporation\n          , \u201cFLEX 10K embedded programmable logic device family, DS-F10K-4.2,\u201d http:\/\/www.altera.com\/literature\/ds\/dsf10k.pdf, January2003."},{"key":"2026032901121504800_ref015","unstructured":"Altera Corporation\n          , \u201cAPEX 20K programmable logic device family data sheet, DS-APEX20K-5.1,\u201d http:\/\/www.altera.com\/literature\/ds\/apex.pdf, March2004."},{"key":"2026032901121504800_ref016","unstructured":"Altera Corporation\n          , \u201cHardCopy structured ASICs,\u201d http:\/\/www.altera.com\/products\/devices\/hardcopy\/hrd-index.html, 2005."},{"key":"2026032901121504800_ref017","unstructured":"Altera Corporation\n          , \u201cMAX II device handbook,\u201d http:\/\/www.altera.com\/literature\/hb\/max2\/max2_mii5v1.pdf, June2005."},{"key":"2026032901121504800_ref018","unstructured":"Altera Corporation\n          , \u201cStratix II device handbook SII5V1-3.1,\u201d http:\/\/www.altera.com\/literature\/lib\/stx2\/stratix2_handbook.pdf, July2005."},{"key":"2026032901121504800_ref019","unstructured":"Altera Corporation\n          , \u201cStratix II GX device handbook SIIGX5V1-1.1,\u201d http:\/\/www.altera.com\/literature\/hb\/stx2gx\/stxiigx_handbook.pdf, October2005."},{"key":"2026032901121504800_ref020","unstructured":"Altera Corporation\n          , \u201cAltera\u2019s strategy for delivering the benefits of the 65-nm semiconductor process WP-01002-1.1,\u201d http:\/\/www.altera.com\/literature\/wp\/wp-01002.pdf, September2006."},{"key":"2026032901121504800_ref021","unstructured":"Altera Corporation\n          , \u201cCyclone II device handbook, ver. CII5V1-3.0,\u201d http:\/\/www.altera.com\/literature\/hb\/cyc2\/cyc2_cii5v1.pdf, June2006."},{"key":"2026032901121504800_ref022","unstructured":"Altera Corporation\n          , \u201cStratix device family data sheet, Volume 1, S5V1-3.4,\u201d http:\/\/www.altera.com\/literature\/hb\/stx\/stratix_vol_1.pdf, January2006."},{"key":"2026032901121504800_ref023","unstructured":"Altera Corporation\n          , \u201cStratix III device handbook, ver 1.0,\u201d http:\/\/www.altera.com\/literature\/hb\/stx3\/stratix3_handbook.pdf, November2006."},{"key":"2026032901121504800_ref024","unstructured":"Altera Corporation\n          , \u201cCyclone device handbook. C5V1-2.1, ver. C5V1-2.1,\u201d http:\/\/www.altera.com\/literature\/hb\/cyc\/cyc_c5v1.pdf, January2007."},{"key":"2026032901121504800_ref025","unstructured":"Altera Corporation\n          , \u201cCyclone III device handbook, ver. CIII5V1-1.2,\u201d http:\/\/www.altera.com\/literature\/hb\/cyc3\/cyclone3_handbook.pdf, September2007."},{"key":"2026032901121504800_ref026","unstructured":"Altera Corporation\n          , \u201cRobust SEU mitigation with Stratix III FPGAs, WP-01012-1.0,\u201d http:\/\/www.altera.com\/literature\/wp\/wp-01012.pdf, October2007."},{"key":"2026032901121504800_ref027","unstructured":"Altera Corporation\n          , \u201cStratix III FPGAs vs. Xilinx Virtex-5 devices: Architecture and performance comparison, Altera White Paper WP-01007-2.1,\u201d http:\/\/www.altera.com\/literature\/wp\/wp-01007.pdf, October2007."},{"key":"2026032901121504800_ref028","unstructured":"AMI Semiconductor\n          , \u201cStructured digital products,\u201d http:\/\/www.amis.com\/pdf\/structured_digital_brochure.pdf, September2003."},{"key":"2026032901121504800_ref029","first-page":"719","article-title":"A novel low-power FPGA routing switch","author":"Anderson"},{"key":"2026032901121504800_ref030","volume-title":"Circuits, Interconnection, and Packaging for VLSI","author":"Bakaglu","year":"1990"},{"issue":"3","key":"2026032901121504800_ref031","doi-asserted-by":"crossref","first-page":"258","DOI":"10.1109\/MDT.2005.69","article-title":"Soft errors in advanced computer systems","volume":"22","author":"Baumann","year":"2005","journal-title":"IEEE Design and Test of Computers"},{"key":"2026032901121504800_ref032","first-page":"12","article-title":"Embedded floating-point units in FPGAs","author":"Beauchamp","year":"2006"},{"key":"2026032901121504800_ref033","first-page":"10","article-title":"Improving FPGA performance via the use of architecture families","author":"Betz","year":"1995"},{"issue":"1","key":"2026032901121504800_ref034","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1109\/54.655177","article-title":"How much logic should go in an FPGA logic block?","volume":"15","author":"Betz","year":"1998","journal-title":"IEEE Design and Test of Computers"},{"key":"2026032901121504800_ref035","first-page":"171","article-title":"Circuit design, transistor sizing and wire layout of FPGA interconnect","author":"Betz","year":"1999"},{"key":"2026032901121504800_ref036","first-page":"140","article-title":"FPGA routing architecture: Segmentation and buffering to optimize speed and density","author":"Betz"},{"key":"2026032901121504800_ref037","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-5145-4","volume-title":"Architecture and CAD for Deep-Submicron FPGAs","author":"Betz","year":"1999"},{"issue":"7","key":"2026032901121504800_ref038","doi-asserted-by":"crossref","first-page":"561","DOI":"10.1016\/0026-2692(92)90067-B","article-title":"A very-high-speed field-programmable gate array using metal-to-metal antifuse programmable elements","volume":"23","author":"Birkner","year":"1992","journal-title":"Microelectronics Journal"},{"key":"2026032901121504800_ref039","volume-title":"Programmable array logic circuit","author":"Birkner","year":"1978"},{"key":"2026032901121504800_ref040","first-page":"55","article-title":"SEU mitigation for SRAM-based FPGAs through dynamic partial reconfiguration","author":"Bolchini","year":"2007"},{"issue":"2","key":"2026032901121504800_ref041","doi-asserted-by":"crossref","first-page":"183","DOI":"10.1109\/4.982424","article-title":"Impact of die-to-die and within-die parameter fluctuations on themaximum clock frequency distribution for gigascale integration","volume":"37","author":"Bowman","year":"2002","journal-title":"IEEE Journal of Solid-State Circuits"},{"issue":"4","key":"2026032901121504800_ref042","doi-asserted-by":"crossref","first-page":"16","DOI":"10.1109\/54.544532","article-title":"Minimizing FPGA interconnect delays","volume":"13","author":"Brown","year":"1996","journal-title":"IEEE Design and Test of Computers"},{"issue":"2","key":"2026032901121504800_ref043","doi-asserted-by":"crossref","first-page":"42","DOI":"10.1109\/54.500200","article-title":"FPGA and CPLD architectures: A tutorial","volume":"12","author":"Brown","year":"1996","journal-title":"IEEE Design and Test of Computers"},{"issue":"12","key":"2026032901121504800_ref044","doi-asserted-by":"crossref","first-page":"1827","DOI":"10.1109\/43.251146","article-title":"A stochastic model to predict the routability of field-programmable gate arrays","volume":"12","author":"Brown","year":"1993","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"2026032901121504800_ref045","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-3572-0","volume-title":"Field-Programmable Gate Arrays","author":"Brown","year":"1992"},{"issue":"5","key":"2026032901121504800_ref046","doi-asserted-by":"crossref","first-page":"32","DOI":"10.1109\/MM.2007.4378781","article-title":"Synchronization through communication in a massively parallel processor array","volume":"27","author":"Butts","year":"2007","journal-title":"IEEE Micro"},{"key":"2026032901121504800_ref047","first-page":"55","article-title":"A structural object programming model, architecture, chip and tools for reconfigurable computing","author":"Butts"},{"key":"2026032901121504800_ref048","first-page":"138","article-title":"Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs","author":"Campregher","year":"2005"},{"key":"2026032901121504800_ref049","first-page":"233","article-title":"A user programmable reconfiguration gate array","author":"Carter"},{"key":"2026032901121504800_ref050","volume-title":"Redundancy structures and methods in a programmable logic device, US Patent 7,180,324","author":"Chan","year":"2007"},{"issue":"6","key":"2026032901121504800_ref051","doi-asserted-by":"crossref","first-page":"784","DOI":"10.1109\/43.924831","article-title":"Matching-based algorithm for FPGA channel segmentation design","volume":"20","author":"Chang","year":"2001","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"2026032901121504800_ref052","first-page":"80","article-title":"Universal switch-module design for symmetric-array-based FPGAs","author":"Chang"},{"issue":"1","key":"2026032901121504800_ref053","doi-asserted-by":"crossref","first-page":"80","DOI":"10.1145\/225871.225886","article-title":"Universal switch modules for FPGA design","volume":"1","author":"Chang","year":"1996","journal-title":"ACM Transactions Design Automation Electronic Systems"},{"issue":"3","key":"2026032901121504800_ref054","doi-asserted-by":"crossref","DOI":"10.1561\/1000000003","article-title":"FPGA design automation: A survey","volume":"1","author":"Chen","year":"2006","journal-title":"Foundations and Trends in Electronic Design Automation"},{"key":"2026032901121504800_ref055","first-page":"160","article-title":"A modular 0.8 um technology for high performance dielectric antifuse field programmable gate arrays","author":"Chen","year":"1993"},{"issue":"7","key":"2026032901121504800_ref056","doi-asserted-by":"crossref","first-page":"1211","DOI":"10.1109\/TCAD.2006.888289","article-title":"Device and architecture cooptimization for FPGA power reduction","volume":"26","author":"Cheng","year":"2007","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"2026032901121504800_ref057","first-page":"44","article-title":"FPGA performance optimization via chipwise placement considering process variations","author":"Cheng","year":"2006"},{"key":"2026032901121504800_ref058","article-title":"A datapath oriented architecture for FPGAs","author":"Cherepacha","year":"1994"},{"key":"2026032901121504800_ref059","first-page":"329","article-title":"DP-FPGA: An FPGA architecture optimized for datapaths","volume-title":"VLSI Design","author":"Cherepacha","year":"1996"},{"key":"2026032901121504800_ref060","first-page":"143","article-title":"A million gate PLD with 622 MHz I\/O interface, multiple PLLs and high performance embedded CAM","author":"Cheung"},{"key":"2026032901121504800_ref061","first-page":"611","article-title":"Antifuse structure comparison for field programmable gate arrays","author":"Chiang"},{"key":"2026032901121504800_ref062","volume-title":"Closing the Gap Between ASIC and Custom Tools and Techniques for High-Performance ASIC Design","author":"Chinnery","year":"2002"},{"key":"2026032901121504800_ref063","unstructured":"P.\n              Clarke\n            \n          , \u201cCEO Interview: John Lofton Hold of Achronix,\u201d EE Times, http:\/\/www.eetimes.com\/news\/semi\/showArticle.jhtml?articleID=187002064, May2006."},{"key":"2026032901121504800_ref064","first-page":"315","article-title":"Soft error considerations for deep-submicron CMOS circuit applications","author":"Cohen","year":"1999"},{"key":"2026032901121504800_ref065","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1145\/1044111.1044113","article-title":"Technology mapping and architecture evaluation for k\/m-macrocell-based FPGAs","volume":"10","author":"Cong","year":"2005","journal-title":"TODAES"},{"key":"2026032901121504800_ref066","first-page":"704","article-title":"Delay-optimal technology mapping for FPGAs with heterogeneous LUTs","author":"Cong","year":"1998"},{"key":"2026032901121504800_ref067","first-page":"179","article-title":"Technology mapping for FPGAs with embedded memory blocks","author":"Cong"},{"issue":"2","key":"2026032901121504800_ref068","doi-asserted-by":"crossref","first-page":"603","DOI":"10.1109\/JSSC.1985.1052353","article-title":"An EEPROM for microprocessors and custom logic","volume":"20","author":"Cuppens","year":"1985","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"2026032901121504800_ref069","first-page":"127","article-title":"Design of programmable interconnect for sublithographic programmable logic arrays","author":"DeHon","year":"2005"},{"issue":"2","key":"2026032901121504800_ref070","doi-asserted-by":"crossref","first-page":"109","DOI":"10.1145\/1084748.1084750","article-title":"Nanowire-based programmable architectures","volume":"1","author":"Dehon","year":"2005","journal-title":"Journal on Emerging Technologies in Computing Systems"},{"key":"2026032901121504800_ref071","first-page":"123","article-title":"Nanowire-based sublithographic programmable logic arrays","author":"DeHon","year":"2004"},{"issue":"3","key":"2026032901121504800_ref072","doi-asserted-by":"crossref","first-page":"152","DOI":"10.1147\/rd.252.0152","article-title":"Wire length distribution for placements of computer logic","volume":"25","author":"Donath","year":"1981","journal-title":"IBM Journal of Research and Development"},{"key":"2026032901121504800_ref073","first-page":"134","article-title":"Design of switching blocks tolerating defects\/faults in FPGA interconnection resources","author":"Doumar","year":"2000"},{"key":"2026032901121504800_ref074","first-page":"56","article-title":"Statistical circuit modeling and optimization","author":"Duvall","year":"2000"},{"key":"2026032901121504800_ref075","first-page":"307","article-title":"Assessing carbon nanotube bundle interconnect for future FPGA architectures","author":"Eachempati","year":"2007"},{"key":"2026032901121504800_ref076","unstructured":"eASIC Corporation\n          , \u201cNextreme Structured ASIC,\u201d http:\/\/www.easic.com\/pdf\/asic\/nextreme_asic_structured_asic.pdf."},{"key":"2026032901121504800_ref077","first-page":"126","article-title":"RaPiD\u2013reconfigurable pipelined datapath","author":"Ebeling","year":"1996"},{"issue":"2","key":"2026032901121504800_ref078","doi-asserted-by":"crossref","first-page":"127","DOI":"10.1109\/TCS.1981.1084958","article-title":"Two-dimensional stochastic model for interconnections in master slice integrated circuits","volume":"28","author":"El Gamal","year":"1981","journal-title":"IEEE Transactions on Circuits and Systems"},{"issue":"2","key":"2026032901121504800_ref079","doi-asserted-by":"crossref","first-page":"394","DOI":"10.1109\/4.18600","article-title":"An architecture for electrically configurable gate arrays","volume":"24","author":"El Gamal","year":"1989","journal-title":"IEEE Journal of Solid-State Circuits"},{"issue":"12","key":"2026032901121504800_ref080","doi-asserted-by":"crossref","first-page":"1637","DOI":"10.1109\/TCAD.2003.819430","article-title":"On optimal hyperuniversal and rearrangeable switch box designs","volume":"22","author":"Fan","year":"2003","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"2026032901121504800_ref081","first-page":"80","article-title":"A fully-decoded 2048-bit electrically programmable MOS ROM","author":"Frohman-Dentchkowsky"},{"key":"2026032901121504800_ref082","first-page":"145","article-title":"A dual-VDD low power FPGA architecture","author":"Gayasen"},{"key":"2026032901121504800_ref083","first-page":"921","article-title":"Exploring technology alternatives for nano-scale FPGA interconnects","author":"Gayasen","year":"2005"},{"key":"2026032901121504800_ref084","first-page":"188","article-title":"The design of a low energy FPGA","author":"George"},{"key":"2026032901121504800_ref085","first-page":"433","article-title":"Molecular electronics: Devices, systems and tools for gigagate, gigabit chips","author":"Goldstein","year":"2002"},{"issue":"4","key":"2026032901121504800_ref086","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1109\/2.839324","article-title":"PipeRench: A reconfigurable architecture and compiler","volume":"33","author":"Goldstein","year":"2000","journal-title":"Computer"},{"key":"2026032901121504800_ref087","first-page":"330","article-title":"Single-event-upset (SEU) awareness in FPGA routing","author":"Golshan","year":"2007"},{"key":"2026032901121504800_ref088","first-page":"27","article-title":"Conducting filament of the programmed metal electrode amorphous silicon antifuse","author":"Gordon","year":"1993"},{"key":"2026032901121504800_ref089","first-page":"1","article-title":"Consequences and categories of SRAM FPGA configuration SEUs","author":"Graham","year":"2003"},{"key":"2026032901121504800_ref090","first-page":"1042","article-title":"Antifuse field programmable gate arrays","author":"Greene"},{"key":"2026032901121504800_ref091","first-page":"567","article-title":"Segmented channel routing","author":"Greene"},{"issue":"4","key":"2026032901121504800_ref092","doi-asserted-by":"crossref","first-page":"576","DOI":"10.1109\/T-ED.1979.19462","article-title":"An electrically alterable nonvolatile memory cell using a floating-gate structure","volume":"26","author":"Guterman","year":"1979","journal-title":"IEEE Transactions on Electron Devices"},{"key":"2026032901121504800_ref093","first-page":"786","article-title":"Dielectric based antifuse for logic and memory IC","author":"Hamdy"},{"key":"2026032901121504800_ref094","first-page":"711","article-title":"Introducing redundancy in field programmable gate arrays","author":"Hatori","year":"1993"},{"issue":"3","key":"2026032901121504800_ref095","doi-asserted-by":"crossref","first-page":"60","DOI":"10.1109\/MDT.1994.303848","article-title":"An FPGA for implementing asynchronous circuits","volume":"11","author":"Hauck","year":"1994","journal-title":"IEEE Design and Test of Computers"},{"issue":"2","key":"2026032901121504800_ref096","doi-asserted-by":"crossref","first-page":"138","DOI":"10.1109\/92.831434","article-title":"High-performance carry chains for FPGAs","volume":"8","author":"Hauck","year":"2000","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"2026032901121504800_ref097","first-page":"741","article-title":"Advantages of heterogeneous logic block architectures for FPGAs","author":"He"},{"key":"2026032901121504800_ref098","volume-title":"Computer Architecture: A Quantitative Approach","author":"Hennessy","year":"2003"},{"key":"2026032901121504800_ref099","first-page":"45","article-title":"Virtual embedded blocks: A methodology for evaluating embedded elements in FPGAs","author":"Ho","year":"2006"},{"key":"2026032901121504800_ref100","first-page":"36","article-title":"Implementing asynchronous circuits on LUT based FPGAs","author":"Ho","year":"2002"},{"issue":"1","key":"2026032901121504800_ref101","doi-asserted-by":"crossref","first-page":"12","DOI":"10.1109\/40.653013","article-title":"High-speed electrical signalling: Overview and limitations","volume":"18","author":"Horowitz","year":"1998","journal-title":"IEEE Micro"},{"issue":"5","key":"2026032901121504800_ref102","doi-asserted-by":"crossref","first-page":"51","DOI":"10.1109\/MM.2007.4378783","article-title":"A 5-GHz mesh interconnect for a teraflops processor","volume":"27","author":"Hoskote","year":"2007","journal-title":"IEEE Micro"},{"key":"2026032901121504800_ref103","doi-asserted-by":"crossref","article-title":"Third-generation architecture boosts speed and density of field-programmable gate arrays","author":"Hsieh","DOI":"10.1109\/CICC.1990.124841"},{"key":"2026032901121504800_ref104","first-page":"137","article-title":"Column-based precompiled configuration techniques for FPGA fault tolerance","author":"Huang","year":"2001"},{"key":"2026032901121504800_ref105","first-page":"281","article-title":"Moats and drawbridges: An isolation primitive for reconfigurable hardware based systems","author":"Huffmire"},{"key":"2026032901121504800_ref106","unstructured":"M.\n              Hutton\n            , D.Lewis, B.Pedersen, J.Schleicher, R.Yuan, G.Baeckler, A.Lee, R.Saini, and H.Kim, \u201cFracturable FPGA logic elements,\u201d CP-01006-1.0 http:\/\/www.altera.com\/literature\/cp\/cp-01006.pdf."},{"key":"2026032901121504800_ref107","first-page":"3","article-title":"Interconnect enhancements for a high-speed PLD architecture","author":"Hutton"},{"key":"2026032901121504800_ref108","unstructured":"International Technology Roadmap for Semiconductors 2007\n           Edition http:\/\/www.irtrs.net\/reports.html, December2007."},{"key":"2026032901121504800_ref109","first-page":"1","article-title":"Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters","author":"Jamieson"},{"key":"2026032901121504800_ref110","first-page":"688","article-title":"Studying a GALS FPGA architecture using a parameterized automatic design flow","author":"Jia","year":"2006"},{"key":"2026032901121504800_ref111","first-page":"596","article-title":"A yield and speed enhancement scheme under within-die variations on 90 nm LUT array","author":"Katsuki","year":"2005"},{"key":"2026032901121504800_ref112","first-page":"1","article-title":"Hybrid FPGA architecture","author":"Kaviani"},{"issue":"2","key":"2026032901121504800_ref113","doi-asserted-by":"crossref","first-page":"74","DOI":"10.1109\/54.765206","article-title":"The hybrid field-programmable architecture","volume":"16","author":"Kaviani","year":"1999","journal-title":"IEEE Design and Test of Computers"},{"key":"2026032901121504800_ref114","doi-asserted-by":"crossref","DOI":"10.1109\/ISSCC.1981.1156267","article-title":"Redundancy techniques for fast static RAMs","author":"Kokkonen","year":"1981"},{"key":"2026032901121504800_ref115","first-page":"54","article-title":"PCA-1: A fully asynchronous, self-reconfigurable LSI","author":"Konishi","year":"2001"},{"key":"2026032901121504800_ref116","first-page":"6121","article-title":"FPGA performance vs. cell granularity","author":"Kouloheris"},{"key":"2026032901121504800_ref117","first-page":"9","article-title":"FPGA area versus cell granularity \u2014 lookup tables and PLA cells","author":"Kouloheris"},{"key":"2026032901121504800_ref118","article-title":"FPGA area versus cell granularity \u2014 PLA cells","author":"Kouloheris"},{"key":"2026032901121504800_ref119","first-page":"21","article-title":"Measuring the gap between FPGAs and ASICs","author":"Kuon","year":"2006"},{"issue":"2","key":"2026032901121504800_ref120","doi-asserted-by":"crossref","first-page":"203","DOI":"10.1109\/TCAD.2006.884574","article-title":"Measuring the gap between FPGAs and ASICs","volume":"26","author":"Kuon","year":"2007","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"2026032901121504800_ref121","first-page":"105","article-title":"Efficiently supporting fault-tolerance in FPGAs","author":"Lach","year":"1998"},{"key":"2026032901121504800_ref122","first-page":"101","article-title":"FPGA clock network architecture: Flexibility vs. area and power","author":"Lamoureux","year":"2006"},{"key":"2026032901121504800_ref123","first-page":"1469","article-title":"On a pin versus block relationship for partitions of a logic graph","volume-title":"IEEE Transactions on Computers","author":"Landman","year":"1971"},{"key":"2026032901121504800_ref124","unstructured":"Lattice Semiconductor Corporation\n          , \u201cLatticeECP\/EC family data sheet, version 02.0,\u201d http:\/\/www.latticesemi.com\/lit\/docs\/datasheets\/fpga\/ecp_ec_datasheet.pdf, September2005."},{"key":"2026032901121504800_ref125","unstructured":"Lattice Semiconductor Corporation\n          , \u201cLatticeXP family data sheet, version 03.1,\u201d http:\/\/www.latticeseird.com\/lit\/docs\/datasheets\/fpga\/xp_data_sheet.pdf, September2005."},{"key":"2026032901121504800_ref126","unstructured":"Lattice Semiconductor Corporation\n          , \u201cMachXO family data sheet, version 01.2,\u201d http:\/\/www.latticesemi.com\/lit\/docs\/datasheets\/cpld\/machxo.pdf, November2005."},{"key":"2026032901121504800_ref127","unstructured":"Lattice Semiconductor Corporation\n          , \u201cLatticeSC family data sheet DS1004 version 01.5,\u201d http:\/\/www.latticesemi.com\/dynamic\/viewdocument.cfm?document_id=19028, March2007."},{"key":"2026032901121504800_ref128","first-page":"41","article-title":"Directional and single-driver wires in FPGA interconnect","author":"Lemieux"},{"key":"2026032901121504800_ref129","first-page":"59","article-title":"Using sparse crossbars within LUT clusters","author":"Lemieux"},{"key":"2026032901121504800_ref130","first-page":"122","article-title":"Analytical framework for switch block design","author":"Lemieux"},{"key":"2026032901121504800_ref131","first-page":"19","article-title":"Circuit design of routing switches","author":"Lemieux"},{"key":"2026032901121504800_ref132","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-4941-0","volume-title":"Design and Interconnection Networks for Programmable Logic","author":"Lemieux","year":"2004"},{"key":"2026032901121504800_ref133","first-page":"49","article-title":"Cyclone: A low-cost, high-performance FPGA","author":"Leventis","year":"2003"},{"key":"2026032901121504800_ref134","first-page":"443","article-title":"MAX II: A low-cost, highperformance LUT-based CPLD","author":"Leventis"},{"key":"2026032901121504800_ref135","first-page":"14","article-title":"The Stratix II logic and routing architecture","author":"Lewis","year":"2005"},{"key":"2026032901121504800_ref136","first-page":"12","article-title":"The Stratix\u2122 routing and logic architecture","author":"Lewis","year":"2003"},{"key":"2026032901121504800_ref137","article-title":"Vdd programmability to reduce FPGA interconnect power","author":"Li","year":"2004"},{"issue":"11","key":"2026032901121504800_ref138","doi-asserted-by":"crossref","first-page":"1712","DOI":"10.1109\/TCAD.2005.852293","article-title":"Power modeling and characteristics of field programmable gate arrays","volume":"24","author":"Li","year":"2005","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"2026032901121504800_ref139","first-page":"3","article-title":"A routing fabric for monolithically stacked 3D-FPGA","author":"Lin","year":"2007"},{"issue":"2","key":"2026032901121504800_ref140","doi-asserted-by":"crossref","first-page":"216","DOI":"10.1109\/TCAD.2006.887920","article-title":"Performance benefits of mono-lithically stacked 3\u2013D FPGA","volume":"26","author":"Lin","year":"2007","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"2026032901121504800_ref141","first-page":"199","article-title":"Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability","author":"Lin"},{"key":"2026032901121504800_ref142","first-page":"239","article-title":"A high density flash memory FPGA family","author":"Lipp"},{"key":"2026032901121504800_ref143","first-page":"136","article-title":"Cascading switching networks of two-input flexible cells","volume-title":"IEEE Transactions on Electronic Computing","author":"Maitra","year":"1962"},{"key":"2026032901121504800_ref144","doi-asserted-by":"crossref","DOI":"10.1109\/CICC.1992.591107","article-title":"An MPGA compatible FPGA architecture","author":"Marple","year":"1992"},{"key":"2026032901121504800_ref145","first-page":"135","article-title":"A reconfigurable arithmetic array for multimedia applications","author":"Marshall","year":"1999"},{"key":"2026032901121504800_ref146","first-page":"274","article-title":"A new switch block for segmented FPGAs","author":"Masud"},{"key":"2026032901121504800_ref147","first-page":"169","article-title":"Performance and yield enhancement of FPGAs with within-die variation using multiple configurations","author":"Matsumoto","year":"2007"},{"key":"2026032901121504800_ref148","volume-title":"Redundancy circuitry for logic circuits","author":"McClintock","year":"2000"},{"issue":"1","key":"2026032901121504800_ref149","doi-asserted-by":"crossref","first-page":"78","DOI":"10.1109\/TNANO.2002.1005429","article-title":"Single-walled carbon nanotube electronics","volume":"1","author":"McEuen","year":"2002","journal-title":"IEEE Transactions on Nanotechnology"},{"key":"2026032901121504800_ref150","doi-asserted-by":"crossref","first-page":"203","DOI":"10.1145\/321386.321387","article-title":"A survey of microcellular research","volume":"14","author":"Minnick","year":"1967","journal-title":"Journal of the Association of Computing Machinery"},{"key":"2026032901121504800_ref151","first-page":"624","article-title":"An adaptive FPGA architecture with process variation compensation and reduced leakage","author":"Nabaa","year":"2006"},{"key":"2026032901121504800_ref152","first-page":"499","article-title":"An SRAM-programmable field-configurable memory","author":"Ngai"},{"key":"2026032901121504800_ref153","first-page":"3","article-title":"A novel predictable segmented FPGA routing architectures","author":"Ochetta"},{"key":"2026032901121504800_ref154","first-page":"90","article-title":"Design methodology and tools for NEC electronics\u00c4 structured ASIC ISSP","author":"Okamoto","year":"2004"},{"key":"2026032901121504800_ref155","first-page":"184","article-title":"An architectural exploration of via patterned gate arrays","author":"Patel","year":"2003"},{"issue":"8","key":"2026032901121504800_ref156","doi-asserted-by":"crossref","first-page":"1248","DOI":"10.1109\/5.622505","article-title":"Flash memory cells-an overview","volume":"85","author":"Pavan","year":"1997","journal-title":"Proceedings of the IEEE"},{"key":"2026032901121504800_ref157","doi-asserted-by":"crossref","first-page":"21","DOI":"10.1007\/3-540-60294-1_95","volume-title":"Field-Programmable Logic and Applications","author":"Payne","year":"1995"},{"issue":"5","key":"2026032901121504800_ref158","doi-asserted-by":"crossref","first-page":"282","DOI":"10.1049\/ip-cdt:19960655","article-title":"Asynchronous FPGA architectures","volume":"143","author":"Payne","year":"1996","journal-title":"IEEE Proceedings Computers and Digital Techniques"},{"key":"2026032901121504800_ref159","first-page":"230","article-title":"Architecture and routability analysis for row-based FPGAs","author":"Pedram"},{"key":"2026032901121504800_ref160","volume-title":"ERA60100 preliminary data sheet","author":"Plessey Semiconductor","year":"1989"},{"key":"2026032901121504800_ref161","unstructured":"QuickLogic Corporation\n          , \u201cEclipse II family data sheet (Rev P),\u201d http:\/\/rwww.quicklogic.com\/images\/EclipseILFamily_DS.pdf, February2007."},{"key":"2026032901121504800_ref162","unstructured":"QuickLogic Corporation\n          , \u201cQuickLogic PolarPro Data Sheet (Rev H),\u201d http:\/\/www.quicklogic.com\/images\/polarpro_DS.pdf, February2007."},{"key":"2026032901121504800_ref163","volume-title":"Digital Integrated Circuits: A Design Perspective","author":"Rabaey","year":"1996"},{"key":"2026032901121504800_ref164","first-page":"23","article-title":"Evaluation of low-leakage design techniques for field programmable gate arrays","author":"Rahman"},{"key":"2026032901121504800_ref165","first-page":"59","article-title":"Nearest neighbour interconnect architecture in deep submicron FPGAs","author":"Roopchansingh"},{"issue":"3","key":"2026032901121504800_ref166","doi-asserted-by":"crossref","first-page":"277","DOI":"10.1109\/4.75006","article-title":"Flexibility of interconnection structures for field-programmable gate arrays","volume":"26","author":"Rose","year":"1991","journal-title":"IEEE Journal of Solid-State Circuits"},{"issue":"7","key":"2026032901121504800_ref167","doi-asserted-by":"crossref","first-page":"1013","DOI":"10.1109\/5.231340","article-title":"Architecture of field-programmable gate arrays","volume":"81","author":"Rose","year":"1993","journal-title":"Proceedings of the IEEE"},{"key":"2026032901121504800_ref168","doi-asserted-by":"crossref","article-title":"The effect of logic block complexity on area of programmable gate arrays","author":"Rose","DOI":"10.21236\/ADA207172"},{"issue":"5","key":"2026032901121504800_ref169","doi-asserted-by":"crossref","first-page":"1217","DOI":"10.1109\/4.62145","article-title":"Architecture of field-programmable gate arrays: The effect of logic block functionality on area efficiency","volume":"25","author":"Rose","year":"1990","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"2026032901121504800_ref170","article-title":"Optimization of channel segmentation for channeled architecture FPGAs","author":"Roy"},{"key":"2026032901121504800_ref171","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-540-45234-8_35","article-title":"Globally asynchronous locally synchronous FPGA architectures","author":"Royal","year":"2003"},{"key":"2026032901121504800_ref172","volume-title":"Programmable logic device having regions of non-repairable circuitry within an array of repairable circuitry and associated configuration hardware and method","author":"Saini","year":"2007"},{"key":"2026032901121504800_ref173","first-page":"323","article-title":"Implementation of dynamically reconfigurable processor DAPDNA-2","author":"Sato","year":"2005"},{"issue":"3","key":"2026032901121504800_ref174","doi-asserted-by":"crossref","first-page":"353","DOI":"10.1109\/JSSC.1980.1051398","article-title":"A two-transistor SIMOS EAROM cell","volume":"15","author":"Scheibe","year":"1980","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"2026032901121504800_ref175","first-page":"63","article-title":"PipeRench: A virtualized programmable datapath in 0.18 micron technology","author":"Schmit","year":"2002"},{"key":"2026032901121504800_ref176","first-page":"97","article-title":"Within-die delay variability in 90 nm FPGAs and beyond","author":"Sedcole","year":"2006"},{"key":"2026032901121504800_ref177","first-page":"178","article-title":"Parametric yield in FPGAs due to withindie delay variations: A quantitative analysis","author":"Sedcole","year":"2007"},{"key":"2026032901121504800_ref178","first-page":"157","article-title":"Dynamic power consumption in Virtex-II FPGA family","author":"Shang"},{"key":"2026032901121504800_ref179","first-page":"75","article-title":"Mixing buffers and pass transistors in FPGA routing architectures","author":"Sheng"},{"key":"2026032901121504800_ref180","first-page":"97102","article-title":"Design considerations for regular fabrics","author":"Sherlekar","year":"2004"},{"key":"2026032901121504800_ref181","first-page":"25","article-title":"Characterization and modeling of a highly reliable metal-to-metal antifuse for high-performance and high-density field-programmable gate arrays","author":"Shih","year":"1997"},{"key":"2026032901121504800_ref182","first-page":"2330","article-title":"FPGA interconnect planning","author":"Singh"},{"key":"2026032901121504800_ref183","first-page":"161","article-title":"The case for registered routing switches in field programmable gate arrays","author":"Singh"},{"key":"2026032901121504800_ref184","first-page":"71","article-title":"Variation-aware routing for FPGAs","author":"Sivaswamy","year":"2007"},{"key":"2026032901121504800_ref185","first-page":"21","article-title":"HARP: hard-wired routing pattern FPGAs","author":"Sivaswamy"},{"key":"2026032901121504800_ref186","article-title":"0.25 um flash memory based FPGA for space applications","author":"Speers","year":"1999"},{"issue":"11","key":"2026032901121504800_ref187","doi-asserted-by":"crossref","first-page":"1940","DOI":"10.1109\/JPROC.2003.818327","article-title":"Molecular electronics: From devices and interconnect to circuits and architecture","volume":"91","author":"Stan","year":"2003","journal-title":"Proceedings of the IEEE"},{"key":"2026032901121504800_ref188","unstructured":"Stretch Inc\n          , \u201cStretch S5530 product brief, MK-5530C-0002-000,\u201d http:\/\/www.stretchinc.com\/_files\/Stretc_S5530_Softwar_Configurabl_Processor.pdf, 2005."},{"key":"2026032901121504800_ref189","unstructured":"Stretch Inc\n          , \u201cS6100\/S6105 product brief, MK-6000C-0001-000,\u201d http:\/\/www.stretchinc.com\/_files\/S6000.pdf, 2007."},{"issue":"6","key":"2026032901121504800_ref190","doi-asserted-by":"crossref","first-page":"888","DOI":"10.1088\/0957-4484\/16\/6\/045","article-title":"CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices","volume":"16","author":"Strukov","year":"2005","journal-title":"Nanotechnology"},{"key":"2026032901121504800_ref191","first-page":"131","article-title":"A reconfigurable architecture for hybrid CMOS\/Nanodevice circuits","author":"Strukov","year":"2006"},{"issue":"2","key":"2026032901121504800_ref192","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1109\/MM.2002.997877","article-title":"The Raw microprocessor: A computational fabric for software circuits and generalpurpose programs","volume":"22","author":"Taylor","year":"2002","journal-title":"IEEE Micro"},{"issue":"11","key":"2026032901121504800_ref193","doi-asserted-by":"crossref","first-page":"1376","DOI":"10.1109\/TC.2004.88","article-title":"An asynchronous dataflow FPGA architecture","volume":"53","author":"Teifel","year":"2004","journal-title":"IEEE Transactions on Computers"},{"key":"2026032901121504800_ref194","first-page":"133","article-title":"Highly pipelined asynchronous FPGAs","author":"Teifel","year":"2004"},{"key":"2026032901121504800_ref195","unstructured":"Triscend Corporation\n          , \u201cTriscend A7V MKT012-0001-001,\u201d http:\/\/www.zylogic.com.cn\/download\/pdf\/products01_2\/A7VProductBrief.pdf."},{"key":"2026032901121504800_ref196","unstructured":"Triscend Corporation\n          , \u201cTriscend E5 configurable system-on-chip platform product description TCH300-0001-001,\u201d http:\/\/www.keil.com\/dd\/docs\/datashts\/triscend\/te5xx.pdf, 2001."},{"key":"2026032901121504800_ref197","first-page":"125","article-title":"HSRA: High-speed, hierarchical synchronous reconfigurable array","author":"Tsu"},{"key":"2026032901121504800_ref198","first-page":"57","article-title":"Leakage power analysis of a 90 nm FPGA","author":"Tuan"},{"key":"2026032901121504800_ref199","volume-title":"Programmable logic devices with stabilized configuration cells for reduced soft error rates","author":"Turner","year":"2005"},{"issue":"9","key":"2026032901121504800_ref200","doi-asserted-by":"crossref","first-page":"1829","DOI":"10.1109\/JSSC.2005.852156","article-title":"A 90-nm FPGA I\/O buffer design with 1.6-Gb\/s data rate for source-synchronous system and 300MHz clock rate for external memory interface","volume":"40","author":"Tyhach","year":"2005","journal-title":"IEEE Journal of Solid-State Circuits"},{"issue":"1","key":"2026032901121504800_ref201","doi-asserted-by":"crossref","first-page":"29","DOI":"10.1109\/JSSC.2007.910957","article-title":"An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS","volume":"43","author":"Vangal","year":"2008","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"2026032901121504800_ref202","volume-title":"Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets","author":"Voogel","year":"2006"},{"key":"2026032901121504800_ref203","first-page":"90","article-title":"Programmable logic arrays \u2014 cheaper by the millions","volume":"40","author":"Wahlstrom","year":"1967","journal-title":"Electronics"},{"key":"2026032901121504800_ref204","first-page":"3","article-title":"The SFRA: A corner-turn FPGA architecture","author":"Weaver"},{"key":"2026032901121504800_ref205","volume-title":"Application-specific testing methods for programmable logic devices","author":"Wells","year":"2005"},{"issue":"5","key":"2026032901121504800_ref206","doi-asserted-by":"crossref","first-page":"15","DOI":"10.1109\/MM.2007.4378780","article-title":"On-chip interconnection architecture of the Tile processor","volume":"27","author":"Wentzlaff","year":"2007","journal-title":"IEEE Micro"},{"issue":"1","key":"2026032901121504800_ref207","doi-asserted-by":"crossref","first-page":"114","DOI":"10.1109\/JSSC.1987.1052682","article-title":"On the design of a redundant programmable logic array RPLA","volume":"22","author":"Wey","year":"1987","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"2026032901121504800_ref208","volume-title":"Architectures and Algorithms for Field-Programmable Gate Arrays with Embedded Memories","author":"Wilton","year":"1997"},{"key":"2026032901121504800_ref209","first-page":"97","article-title":"Architecture of centralized field-configurable memory","author":"Wilton","year":"1995"},{"key":"2026032901121504800_ref210","doi-asserted-by":"crossref","article-title":"Implementing logic in FPGA embedded memory arrays: Architectural implications","author":"Wilton","DOI":"10.1109\/CICC.1998.694978"},{"key":"2026032901121504800_ref211","first-page":"171","article-title":"SMAP: Heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays","author":"Wilton"},{"issue":"1","key":"2026032901121504800_ref212","doi-asserted-by":"crossref","first-page":"56","DOI":"10.1109\/43.822620","article-title":"Heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays","volume":"19","author":"Wilton","year":"2000","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"2026032901121504800_ref213","first-page":"142","article-title":"Implementing logic in FPGA memory arrays: Heterogeneous memory architectures","author":"Wilton"},{"issue":"2","key":"2026032901121504800_ref214","doi-asserted-by":"crossref","first-page":"485","DOI":"10.1109\/JSSC.2004.841038","article-title":"Design considerations for soft embedded programmable logic cores","volume":"40","author":"Wilton","year":"2005","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"2026032901121504800_ref215","first-page":"170","article-title":"An architecture for asynchronous FPGAs","author":"Wong","year":"2003"},{"key":"2026032901121504800_ref216","first-page":"19","article-title":"FPGA device and architecture evaluation considering process variations","author":"Wong","year":"2005"},{"key":"2026032901121504800_ref217","doi-asserted-by":"crossref","article-title":"A 5000-gate CMOS EPLD with multiple logic and interconnect arrays","author":"Wong","DOI":"10.1109\/CICC.1989.56697"},{"key":"2026032901121504800_ref218","first-page":"90","article-title":"Revisiting the cascade circuit in logic cells of lookup table based FPGAs","author":"Woo","year":"1995"},{"key":"2026032901121504800_ref219","first-page":"103","article-title":"Structured ASIC, evolution or revolution?","author":"Wu","year":"2004"},{"key":"2026032901121504800_ref220","first-page":"568","article-title":"Orthogonal greedy coupling \u2014 anew optimization approach for 2-D field-programmable gate arrays","author":"Wu"},{"key":"2026032901121504800_ref221","unstructured":"Xilinx\n          , \u201cSpartan-II 2.5V FPGA family complete data sheet,\u201d http:\/\/direct.xilinx.com\/bvdocs\/publications\/ds001.pdf."},{"key":"2026032901121504800_ref222","unstructured":"Xilinx\n          , \u201cXilinx 3000 series data sheet,\u201d http:\/\/direct.xilinx.com\/bvdocs\/publications\/3000.pdf."},{"key":"2026032901121504800_ref223","unstructured":"Xilinx\n          , \u201cXilinx: EasyPath series overview,\u201d http:\/\/www.xilinx.com\/products\/silicon_solutions\/fpgas\/easypath\/overview.htm."},{"key":"2026032901121504800_ref224","unstructured":"Xilinx\n          , \u201cVirtex 2.5V field programmable gate arrays, DS003-1(v2.5),\u201d http:\/\/direct.xilinx.com\/bvdocs\/publications\/ds003-1.pdf, April2001."},{"key":"2026032901121504800_ref225","unstructured":"Xilinx\n          , \u201cSpartan and Spartan-XL families field programmable gate arrays. DS060 (v1.7),\u201d http:\/\/direct.xilinx.com\/bvdocs\/publications\/ds060.pdf, June2002."},{"key":"2026032901121504800_ref226","volume-title":"Xilinx announces acquisition of Triscend Corp","author":"Xilinx","year":"2004"},{"key":"2026032901121504800_ref227","unstructured":"Xilinx\n          , \u201cSpartan-3 FPGA family: Complete data sheet,\u201d DS099, http:\/\/direct.xilinx.com\/bvdocs\/publications\/ds099.pdf, August2005."},{"key":"2026032901121504800_ref228","unstructured":"Xilinx\n          , \u201cVirtex-4 family overview,\u201d DS112(v1.4), http:\/\/direct.xilinx.com\/bvdocs\/publications\/ds112.pdf, June2005."},{"key":"2026032901121504800_ref229","unstructured":"Xilinx\n          , \u201cVirtex-II platform FPGAs: Complete data sheet. DS031(v3.4),\u201d http:\/\/direct.xilinx.com\/bvdocs\/publications\/ds031.pdf, March2005."},{"key":"2026032901121504800_ref230","unstructured":"Xilinx\n          , \u201cTriple module redundancy design techniques for Virtex FPGAs,\u201d Xilinx Application Note 197, www.xilinx.com\/support\/documentation\/application_notes\/xapp197.pdf, July2006."},{"key":"2026032901121504800_ref231","volume-title":"Virtex-5 user guide","author":"Xilinx","year":"2006"},{"key":"2026032901121504800_ref232","unstructured":"Xilinx\n          , \u201cXC9500 in-system programmable CPLD family DS063(v5.4),\u201d http:\/\/direct.xilinx.com\/bvdocs\/publications\/DS063.pdf, April2006."},{"key":"2026032901121504800_ref233","unstructured":"Xilinx\n          , \u201cPower consumption in 65 nm FPGAs, Xilinx White Paper WP246 (v1.2),\u201d http:\/\/www.xilinx.com\/support\/documentation\/white_papers\/wp246.pdf, February2007."},{"key":"2026032901121504800_ref234","unstructured":"Xilinx\n          , \u201cSpartan-3AN FPGA family data sheet, DS557,\u201d http:\/\/direct.xilinx.com\/bvdocs\/publications\/ds557.pdf, February2007."},{"key":"2026032901121504800_ref235","unstructured":"Xilinx\n          , \u201cVirtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet, DS083(v4.6),\u201d http:\/\/direct.xilinx.com\/bvdocs\/publications\/ds083.pdf, March2007."},{"key":"2026032901121504800_ref236","unstructured":"Xilinx\n          , \u201cXilinx FPGAs overcome the side effects of sub-90nm technology, Xilinx White Paper WP256 v1.0.1,\u201d http:\/\/www.xilinx.com\/support\/documentation\/white_papers\/wp256.pdf, March2007."},{"key":"2026032901121504800_ref237","first-page":"147","article-title":"On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques","author":"Yan","year":"2002"},{"key":"2026032901121504800_ref238","first-page":"3","article-title":"Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits","author":"Ye"},{"key":"2026032901121504800_ref239","volume-title":"FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines","author":"Young","year":"1999"},{"key":"2026032901121504800_ref240","first-page":"255","article-title":"Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement","author":"Yu","year":"2005"},{"key":"2026032901121504800_ref241","first-page":"189","article-title":"FPGA defect tolerance: Impact of granularity","author":"Yu","year":"2005"},{"issue":"8","key":"2026032901121504800_ref242","doi-asserted-by":"crossref","first-page":"310","DOI":"10.1109\/55.296226","article-title":"Metal-to-metal antifuses with very thin silicon dioxide films","volume":"15","author":"Zhang","year":"1994","journal-title":"IEEE Electron Device Letters"},{"key":"2026032901121504800_ref243","first-page":"1290","article-title":"Optimal MST-based graph algorithm on FPGA segmentation design","author":"Zhou"},{"key":"2026032901121504800_ref244","first-page":"480","article-title":"Switch module design with application to two dimensional segmentation design","author":"Zhu"},{"key":"2026032901121504800_ref245","first-page":"187","article-title":"A hybrid ASIC and FPGA architecture","volume-title":"ICCAD \u201902","author":"Zuchowski","year":"2002"}],"container-title":["Foundations and Trends\u00ae in Electronic Design Automation"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.emerald.com\/fteda\/article-pdf\/2\/2\/135\/10865281\/1000000005en.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/www.emerald.com\/fteda\/article-pdf\/2\/2\/135\/10865281\/1000000005en.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,4,29]],"date-time":"2026-04-29T14:13:41Z","timestamp":1777472021000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.emerald.com\/fteda\/article\/2\/2\/135\/1319355\/FPGA-Architecture-Survey-and-Challenges"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,4,18]]},"references-count":245,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2008,4,18]]}},"URL":"https:\/\/doi.org\/10.1561\/1000000005","relation":{},"ISSN":["1551-3939","1551-3947"],"issn-type":[{"value":"1551-3939","type":"print"},{"value":"1551-3947","type":"electronic"}],"subject":[],"published":{"date-parts":[[2008,4,18]]}}}