{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,29]],"date-time":"2026-03-29T10:45:58Z","timestamp":1774781158578,"version":"3.50.1"},"reference-count":145,"publisher":"Emerald","issue":"1","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,8,13]]},"abstract":"<jats:p>The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks is becoming impossible. In static timing analysis process variations and signal integrity issues stretch the timing margins to the point where they become too conservative and result in significant overdesign. Importance and difficulty of such problems push some developers to once again turn to asynchronous alternatives.<\/jats:p>\n                  <jats:p>However, the electronics industry for the most part is still reluctant to adopt asynchronous design (with a few notable exceptions) due to a common belief that we still lack a commercial-quality Electronic Design Automation tools (similar to the synchronous RTL-to-GDSII flow) for asynchronous circuits.<\/jats:p>\n                  <jats:p>The purpose of this paper is to counteract this view by presenting design flows that can tackle large designs without significant changes with respect to synchronous design flow. We are limiting ourselves to four design flows that we believe to be closest to this goal. We start from the Tangram flow, because it is the most commercially proven and it is one of the oldest from a methodological point of view.<\/jats:p>\n                  <jats:p>The other three flows (Null Convention Logic, de-synchronization, and gate-level pipelining) could be considered together as asynchronous re-implementations of synchronous (RTL- or gate-level) specifications. The main common idea is substituting the global clocks by local synchronizations. Their most important aspect is to open the possibility to implement large legacy synchronous designs in an almost \u201cpush button\u201d manner, where all asynchronous machinery is hidden, so that synchronous RTL designers do not need to be re-educated. These three flows offer a trade-off from very low overhead, almost synchronous implementations, to very high performance, extremely robust dual-rail pipelines.<\/jats:p>","DOI":"10.1561\/1000000006","type":"journal-article","created":{"date-parts":[[2007,9,3]],"date-time":"2007-09-03T09:13:32Z","timestamp":1188810812000},"page":"1-133","source":"Crossref","is-referenced-by-count":23,"title":["Design Automation of Real-Life Asynchronous Devices and Systems"],"prefix":"10.1561","volume":"2","author":[{"given":"Alexander","family":"Taubin","sequence":"first","affiliation":[{"name":"Boston University,","place":["USA"]}]},{"given":"Jordi","family":"Cortadella","sequence":"additional","affiliation":[{"name":"Universit\u00e4t Polit\u00e9cnica de Catalunya,","place":["Spain"]}]},{"given":"Luciano","family":"Lavagno","sequence":"additional","affiliation":[{"name":"Politecnico di Torino,","place":["Italy"]}]},{"given":"Alex","family":"Kondratyev","sequence":"additional","affiliation":[{"name":"Cadence Design Systems,","place":["USA"]}]},{"given":"Ad","family":"Peeters","sequence":"additional","affiliation":[{"name":"Handshake Solutions,","place":["The Netherlands"]}]}],"member":"140","published-online":{"date-parts":[[2007,8,13]]},"reference":[{"issue":"7","key":"2026032901121493200_ref001","doi-asserted-by":"crossref","first-page":"1101","DOI":"10.1109\/4.933467","article-title":"A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller","volume":"36","author":"Abrial","year":"2001","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"2026032901121493200_ref002","unstructured":"Achronix Semiconductor\n          , www.achronix.co., 2006."},{"key":"2026032901121493200_ref003","first-page":"10062","article-title":"Statistical timing analysis using bounds","volume-title":"Design, Automation and Test in Europe (DATE)","author":"Agarwal","year":"2003"},{"key":"2026032901121493200_ref004","volume-title":"A Fully Automated Desynchronization Flow for Synchronous Circuits","author":"Andrikos","year":"2006"},{"key":"2026032901121493200_ref005","first-page":"151","article-title":"HW\/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform","author":"Baleani"},{"key":"2026032901121493200_ref006","volume-title":"Implementing Balsa Handshake Circuits","author":"Bardsley","year":"2000"},{"key":"2026032901121493200_ref007","article-title":"Bridging the gap between asynchronous design and designers (Tutorial)","author":"Beerel"},{"key":"2026032901121493200_ref008","first-page":"184","article-title":"Slack matching asynchronous designs","author":"Beerel"},{"key":"2026032901121493200_ref009","first-page":"22","article-title":"Telescopic units: Increasing the average throughput of pipelined designs by adaptive latency control","author":"Benini"},{"key":"2026032901121493200_ref010","volume-title":"Handel-C Language Reference Manual","author":"Celoxica","year":"2003"},{"key":"2026032901121493200_ref011","unstructured":"CeltIC signal integrity analysis\n          , www.cadence.com\/product."},{"key":"2026032901121493200_ref012","article-title":"Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems","author":"Chelcea"},{"key":"2026032901121493200_ref013","volume-title":"Closing the Gap between ASIC & Custom. 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