{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,2]],"date-time":"2026-05-02T22:36:04Z","timestamp":1777761364035,"version":"3.51.4"},"reference-count":195,"publisher":"Emerald","issue":"1-2","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,7,13]]},"abstract":"<jats:p>This manuscript is the first in a two part survey and analysis of the state of the art in secure processor systems, with a specific focus on remote software attestation and software isolation. This manuscript first examines the relevant concepts in computer architecture and cryptography, and then surveys attack vectors and existing processor systems claiming security for remote computation and\/or software isolation. This work examines in detail the modern isolation container (enclave) primitive as a means to minimize trusted software given practical trusted hardware and reasonable performance overhead. Specifically, this work examines in detail the programming model and software design considerations of Intel\u2019s Software Guard Extensions (SGX), as it is an available and documented enclave-capable system.<\/jats:p>\n                  <jats:p>Part II of this work is a deep dive into the implementation and security evaluation of two modern enclave-capable secure processor systems: SGX and MIT\u2019s Sanctum. The complex but insufficient threat model employed by SGX motivates Sanctum, which achieves stronger security guarantees under software attacks with an equivalent programming model.<\/jats:p>\n                  <jats:p>This work advocates a principled, transparent, and well-scrutinized approach to secure system design, and argues that practical guarantees of privacy and integrity for remote computation are achievable at a reasonable design cost and performance overhead.<\/jats:p>","DOI":"10.1561\/1000000051","type":"journal-article","created":{"date-parts":[[2017,7,13]],"date-time":"2017-07-13T06:29:07Z","timestamp":1499927347000},"page":"1-248","source":"Crossref","is-referenced-by-count":28,"title":["Secure Processors Part I: Background, Taxonomy for Secure Enclaves and Intel SGX Architecture"],"prefix":"10.1108","volume":"11","author":[{"given":"Victor","family":"Costan","sequence":"first","affiliation":[{"name":"Massachusetts Institute of Technology Computer Science and Artificial Intelligence Laboratory,"}]},{"given":"Ilia","family":"Lebedev","sequence":"additional","affiliation":[{"name":"Massachusetts Institute of Technology Computer Science and Artificial Intelligence Laboratory,"}]},{"given":"Srinivas","family":"Devadas","sequence":"additional","affiliation":[{"name":"Massachusetts Institute of Technology Computer Science and Artificial Intelligence Laboratory,"}]}],"member":"140","published-online":{"date-parts":[[2017,7,13]]},"reference":[{"key":"2026032901170162500_ref001","volume-title":"FIPS 140-2 Consolidated Validation Certificate No. 0003. 2011. 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