{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,2]],"date-time":"2026-06-02T03:48:33Z","timestamp":1780372113505,"version":"3.54.1"},"reference-count":126,"publisher":"Emerald","issue":"4","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,3,6]]},"abstract":"<jats:p>Over the past decade, a massive proliferation of machine learning algorithms has emerged, from applications for surveillance to self-driving cars. The turning point occurred with the arrival of Convolutional Neural Network (CNN) models and the incredible accuracy brought by Deep Neural Networks (DNNs) at the cost of high computational complexity. In this growing environment, graphic processing units (GPUs) have become the de facto reference platform for the training and inference phases of CNNs and DNNs due to their high processing parallelism and memory bandwidth. However, GPUs are power-hungry architectures. To enable the deployment of CNN and DNN applications on energy-constrained devices (e.g., IoT devices), industry and academic research have moved towards hardware accelerators. Following the evolution of neural networks (from CNNs to DNNs), this survey sheds light on the impact of this architectural shift and discusses hardware accelerator trends in terms of design, exploration, simulation, and frameworks developed in both academia and industry.<\/jats:p>","DOI":"10.1561\/1000000060","type":"journal-article","created":{"date-parts":[[2023,3,6]],"date-time":"2023-03-06T08:22:20Z","timestamp":1678090940000},"page":"270-344","source":"Crossref","is-referenced-by-count":6,"title":["From CNN to DNN Hardware Accelerators: A Survey on Design, Exploration, Simulation, and Frameworks"],"prefix":"10.1108","volume":"13","author":[{"given":"Leonardo Rezende","family":"Juracy","sequence":"first","affiliation":[{"name":"Pontifical Catholic University of Rio Grande do Sul \u2013 PUCRS School of Technology, ,","place":["Brazil"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rafael","family":"Garibotti","sequence":"additional","affiliation":[{"name":"Pontifical Catholic University of Rio Grande do Sul \u2013 PUCRS School of Technology, ,","place":["Brazil"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Fernando Gehm","family":"Moraes","sequence":"additional","affiliation":[{"name":"Pontifical Catholic University of Rio Grande do Sul \u2013 PUCRS School of Technology, ,","place":["Brazil"]}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"140","published-online":{"date-parts":[[2023,3,6]]},"reference":[{"issue":"5","key":"2026032901223553900_ref001","doi-asserted-by":"crossref","first-page":"78","DOI":"10.1109\/MM.2022.3178580","article-title":"Bridging Python to Silicon: The SODA Toolchain","volume":"42","author":"Agostini","year":"2022","journal-title":"IEEE Micro"},{"issue":"2","key":"2026032901223553900_ref002","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3380548","article-title":"FFConv: an FPGA-based accelerator for fast convolution layers in convolutional neural networks","volume":"19","author":"Ahmad","year":"2020","journal-title":"ACM Transactions on Embedded Computing Systems"},{"key":"2026032901223553900_ref003","first-page":"441","volume-title":"Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project","author":"Ajayi","year":"2019"},{"key":"2026032901223553900_ref004","unstructured":"Alibaba\n          . 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