{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,28]],"date-time":"2026-08-28T09:08:24Z","timestamp":1787908104615,"version":"build-2784847793"},"reference-count":79,"publisher":"Emerald","issue":"4","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,1,5]]},"abstract":"<jats:p>The rapid development of integrated circuit (IC) technology, driven by the growing demand for Internet of Things (IoT) devices, cloud computing, and cyber-physical systems, has introduced significant challenges in the design and verification of modern System-on-Chip (SoC) systems. Contemporary SoCs, whether used in desktops or servers, are extremely complex with billions of transistors and often use mixed-core technologies. Designing complex SoCs in modern technologies faces issues in scalability, security, verification, and design optimization, especially as the industry transitions to chipset-based architectures. In this work, we explore the potential of deep learning and generative Artificial Intelligence (AI) to address these challenges, focusing on applications in Register Transfer Level (RTL) code generation, design automation, hardware security, and verification.<\/jats:p>\n                  <jats:p>In this work, we review the state-of-the-art in AI-driven Electronic Design Automation (EDA) tools, examining both open source and commercial platforms that have integrated AI to enhance design efficiency and performance. The work focuses on Al\u2019s role in optimizing power, performance, and area (PPA) metrics, as well as improving hardware security by mitigating threats such as hardware Trojans. In addition, we discuss the implications of adopting AI in SoC workflows and its transformative potential in democratizing hardware design.<\/jats:p>","DOI":"10.1561\/1000000063-1","type":"journal-article","created":{"date-parts":[[2025,5,1]],"date-time":"2025-05-01T04:29:33Z","timestamp":1746073773000},"page":"245-294","source":"Crossref","is-referenced-by-count":5,"title":["Deep Learning and Generative AI for Monolithic and Chiplet SoC Design and Verification: A Survey"],"prefix":"10.1108","volume":"14","author":[{"given":"Imed Ben","family":"Dhaou","sequence":"first","affiliation":[{"name":"Dar Al-Hekma University ,","place":["Saudi Arabia"]},{"name":"University of Turku ,","place":["Finland"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Syhem","family":"Larguech","sequence":"additional","affiliation":[{"name":"Cadence Design Systems ,","place":["USA"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sree Ranjani","family":"Rajendran","sequence":"additional","affiliation":[{"name":"Florida Atlantic University ,","place":["USA"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rajat Subhra","family":"Chakraborty","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Kharagpur ,","place":["India"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hannu","family":"Tenhunen","sequence":"additional","affiliation":[{"name":"University of Turku ,","place":["Finland"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ahmed","family":"Abdelgawad","sequence":"additional","affiliation":[{"name":"Central Michigan University ,","place":["USA"]}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"140","published-online":{"date-parts":[[2025,1,5]]},"reference":[{"key":"2026032901025983900_ref001","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3326334","article-title":"Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project","author":"Ajayi","year":"2019"},{"key":"2026032901025983900_ref002","first-page":"1","article-title":"Neural machine translation by jointly learning to align and translate","author":"Bahdanau","year":"2015"},{"key":"2026032901025983900_ref003","doi-asserted-by":"publisher","first-page":"729","DOI":"10.1109\/ICECS.2002.1046272","article-title":"HIPED: a tool for high-level power estimation of digital signal processing algorithms","author":"Ben Dhaou","year":"2002"},{"key":"2026032901025983900_ref004","volume-title":"Low Power Design Techniques for Deep Submicron Technology with Application to Wireless Transceiver Design","author":"Ben Dhaou","year":"2002"},{"key":"2026032901025983900_ref005","doi-asserted-by":"publisher","first-page":"69812","DOI":"10.1109\/ACCESS.2024.3397775","article-title":"Advancements in Generative AI: A Comprehensive Review of GANs, GPT, Autoencoders, Diffusion Model, and Transformers","volume":"12","author":"Bengesi","year":"2024","journal-title":"IEEE Access"},{"issue":"02","key":"2026032901025983900_ref006","doi-asserted-by":"crossref","first-page":"112","DOI":"10.1109\/MDT.2007.30","article-title":"A survey of hybrid techniques for functional verification","volume":"24","author":"Bhadra","year":"2007","journal-title":"IEEE Design & Test of Computers"},{"issue":"8","key":"2026032901025983900_ref007","doi-asserted-by":"publisher","first-page":"1229","DOI":"10.1109\/JPROC.2014.2334493","article-title":"Hardware Trojan Attacks: Threat Analysis and Countermeasures","volume":"102","author":"Bhunia","year":"2014","journal-title":"Proceedings of the IEEE"},{"key":"2026032901025983900_ref008","volume-title":"The Hardware Trojan War: Attacks, Myths, and Defenses","author":"Bhunia","year":"2017","edition":"1st"},{"issue":"12","key":"2026032901025983900_ref009","doi-asserted-by":"publisher","first-page":"1449","DOI":"10.1109\/43.898826","article-title":"Fundamental CAD algorithms","volume":"19","author":"Breuer","year":"2000","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"2026032901025983900_ref010","unstructured":"Cadence Design Systems\n          . (2025). \u201cAI for Intelligent Design\u201d. URL: https:\/\/www.cadence.com\/en_US\/home\/ai\/overview.html."},{"issue":"3","key":"2026032901025983900_ref011","doi-asserted-by":"publisher","DOI":"10.1145\/3641289","article-title":"A Survey on Evaluation of Large Language Models","volume":"15","author":"Chang","year":"2024","journal-title":"ACM Trans. Intell. Syst. Technol"},{"key":"2026032901025983900_ref012","doi-asserted-by":"crossref","unstructured":"Chen, L., Y.Chen, Z.Chu, W.Fang, T.-Y.Ho, R.Huang, Y.Huang, S.Khan, M.Li, X.Li, Y.Li, Y.Liang, J.Liu, Y.Liu, Y.Lin, G.Luo, Z.Shi, G.Sun, D.Tsaras, R.Wang, Z.Wang, X.Wei, Z.Xie, Q.Xu, C.Xue, J.Yan, J.Yang, B.Yu, M.Yuan, E. F. Y.Young, X.Zeng, H.Zhang, Z.Zhang, Y.Zhao, H.-L.Zhen, Z.Zheng, B.Zhu, K.Zhu, and S.Zou. (2024). \u201cThe Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models\u201d. URL: https:\/\/arxiv.org\/abs\/2403.07257.","DOI":"10.1007\/s11432-024-4155-7"},{"key":"2026032901025983900_ref013","article-title":"Evaluating Large Language Models Trained on Code","volume":"abs\/2107.03374","author":"Chen","year":"2021","journal-title":"CoRR"},{"issue":"10","key":"2026032901025983900_ref014","doi-asserted-by":"publisher","first-page":"3388","DOI":"10.1109\/TCAD.2023.3243544","article-title":"TRouter: Thermal-Driven PCB Routing via Nonlocal Crisscross Attention Networks","volume":"42","author":"Chen","year":"2023","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"5","key":"2026032901025983900_ref015","doi-asserted-by":"crossref","first-page":"7","DOI":"10.1109\/MDAT.2017.2735383","article-title":"Challenges and trends in modern SoC design verification","volume":"34","author":"Chen","year":"2017","journal-title":"IEEE Design & Test"},{"key":"2026032901025983900_ref016","doi-asserted-by":"publisher","first-page":"82434","DOI":"10.1109\/ACCESS.2022.3196347","article-title":"Code Generation Using Machine Learning: A Systematic Review","volume":"10","author":"Dehaerne","year":"2022","journal-title":"IEEE Access"},{"key":"2026032901025983900_ref017","doi-asserted-by":"crossref","first-page":"100379","DOI":"10.1016\/j.cosrev.2021.100379","article-title":"A survey on deep learning and its applications","volume":"40","author":"Dong","year":"2021","journal-title":"Computer Science Review"},{"key":"2026032901025983900_ref018","volume-title":"Methodologies for SOC verification","author":"El Fentis","year":"2020"},{"key":"2026032901025983900_ref019","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-030-04666-8","volume-title":"Machine learning in VLSI computer-aided design","author":"Elfadel","year":"2019"},{"issue":"1","key":"2026032901025983900_ref020","doi-asserted-by":"publisher","first-page":"98","DOI":"10.1109\/TCAD.2008.2009151","article-title":"An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs","volume":"28","author":"Fang","year":"2009","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"8","key":"2026032901025983900_ref021","doi-asserted-by":"publisher","first-page":"1417","DOI":"10.1109\/TCAD.2007.891364","article-title":"A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design","volume":"26","author":"Fang","year":"2007","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"2026032901025983900_ref022","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-26896-0","volume-title":"CAD for hardware security","author":"Farahmandi","year":"2023"},{"key":"2026032901025983900_ref023","first-page":"211","article-title":"CAD for Machine Learning in Hardware Security","author":"Farahmandi","year":"2023"},{"key":"2026032901025983900_ref024","first-page":"1","article-title":"Soc security verification using property checking","author":"Farzana","year":"2019"},{"key":"2026032901025983900_ref025","unstructured":"Freund, K.\n           (2023). \u201cCadence Design is Working with Renesas to Build the World\u2019s First LLM Tool for Up-Front Chip Design\u201d. URL: https:\/\/www.forbes.com\/sites\/karlfreund\/2023\/09\/11\/cadence-design-is-working-with-renesas-to-build-the-worlds-first-llm-tool-for-up-front-chip-design\/?sh=4da0c67b21a4."},{"key":"2026032901025983900_ref026","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/MLCAD48534.2019.9142109","article-title":"A Reinforcement Learning-Based Framework for Solving Physical Design Routing Problem in the Absence of Large Test Sets","author":"Gandhi","year":"2019"},{"issue":"6","key":"2026032901025983900_ref027","doi-asserted-by":"crossref","DOI":"10.3390\/electronics7060081","article-title":"A survey on formal verification techniques for safety-critical systems-on-chip","volume":"7","author":"Grimm","year":"2018","journal-title":"Electronics"},{"key":"2026032901025983900_ref028","doi-asserted-by":"crossref","first-page":"151","DOI":"10.1007\/BF00121125","article-title":"Formal hardware verification methods: A survey","volume":"1","author":"Gupta","year":"1992","journal-title":"Formal Methods in System Design"},{"issue":"1","key":"2026032901025983900_ref029","doi-asserted-by":"publisher","first-page":"32","DOI":"10.1186\/s13677-022-00311-8","article-title":"Cloud-based bug tracking software defects analysis using deep learning","volume":"11","author":"Hai","year":"2022","journal-title":"Journal of Cloud Computing"},{"key":"2026032901025983900_ref030","doi-asserted-by":"publisher","first-page":"484","DOI":"10.1109\/DAC.1983.1585697","article-title":"A Method of Automatic Data Path Synthesis","author":"Hitchcock","year":"1983"},{"issue":"5","key":"2026032901025983900_ref031","doi-asserted-by":"publisher","DOI":"10.1145\/3451179","article-title":"Machine Learning for Electronic Design Automation: A Survey","volume":"26","author":"Huang","year":"2021","journal-title":"ACM Trans. Des. Autom. Electron. Syst"},{"key":"2026032901025983900_ref032","article-title":"Optimizing design verification using machine learning: Doing better than random","volume-title":"arXiv preprint","author":"Hughes","year":"2019"},{"issue":"4","key":"2026032901025983900_ref033","doi-asserted-by":"publisher","DOI":"10.3390\/mi14040828","article-title":"Hardware Trojan Mitigation Technique in Network-on-Chip (NoC)","volume":"14","author":"Hussain","year":"2023","journal-title":"Micromachines"},{"key":"2026032901025983900_ref034","doi-asserted-by":"publisher","first-page":"351","DOI":"10.1109\/ASP-DAC47756.2020.9045734","article-title":"Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools","author":"Kabir","year":"2020"},{"key":"2026032901025983900_ref035","article-title":"Scaling laws for neural language models","volume":"abs\/2001.08361","author":"Kaplan","year":"2020","journal-title":"CoRR"},{"key":"2026032901025983900_ref036","first-page":"197","article-title":"TALIB: an IC layout design assistant","author":"Kim","year":"1983"},{"key":"2026032901025983900_ref037","article-title":"Register verification: Do we have reliable specification?","author":"Kim","year":"2013"},{"key":"2026032901025983900_ref038","doi-asserted-by":"publisher","first-page":"125","DOI":"10.1109\/AFIPS.1985.63","article-title":"The impact of AI technology on VLSI design","author":"Kirk","year":"1985"},{"issue":"2","key":"2026032901025983900_ref039","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3563391","article-title":"A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation","volume":"28","author":"Koblah","year":"2023","journal-title":"ACM transactions on design automation of electronic systems"},{"key":"2026032901025983900_ref040","doi-asserted-by":"publisher","first-page":"479","DOI":"10.1109\/DAC.1983.1585696","article-title":"The VLSI Design Automation Assistant: Prototype System","author":"Kowalski","year":"1983"},{"issue":"1","key":"2026032901025983900_ref041","doi-asserted-by":"crossref","first-page":"23","DOI":"10.5392\/IJoC.2011.7.1.023","article-title":"Analysis of Verification Methodologies Based on a SoC Platform Design","volume":"7","author":"Lee","year":"2011","journal-title":"International Journal of Contents"},{"key":"2026032901025983900_ref042","first-page":"21","article-title":"FVP: A formal verification platform for SoC","author":"Liao","year":"2003"},{"key":"2026032901025983900_ref043","first-page":"170","article-title":"A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs","author":"Lin","year":"2021"},{"issue":"10","key":"2026032901025983900_ref044","doi-asserted-by":"crossref","DOI":"10.1007\/s11432-023-3926-8","article-title":"Review of chiplet-based design: system architecture and interconnection","volume":"67","author":"Liu","year":"2024","journal-title":"Science China. Information sciences"},{"key":"2026032901025983900_ref045","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/LAD62341.2024.10691801","article-title":"VerilogReader: LLM-Aided Hardware Test Generation","author":"Ma","year":"2024"},{"key":"2026032901025983900_ref046","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3656232","article-title":"CDLS: Constraint Driven Generative AI Framework for Analog Layout Synthesis","author":"Mangalagiri","year":"2024"},{"key":"2026032901025983900_ref047","doi-asserted-by":"publisher","first-page":"111","DOI":"10.1109\/FPGA.1995.242049","article-title":"PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs","author":"McMurchie","year":"1995"},{"issue":"3","key":"2026032901025983900_ref048","doi-asserted-by":"publisher","first-page":"479","DOI":"10.1109\/TCAD.2020.3003276","article-title":"RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey","volume":"40","author":"Nasser","year":"2021","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"2026032901025983900_ref049","first-page":"733","article-title":"System-on-chip security architecture and CAD framework for hardware patch","author":"Nath","year":"2018"},{"key":"2026032901025983900_ref050","unstructured":"Naveed, H., A. U.Khan, S.Qiu, M.Saqib, S.Anwar, M.Usman, N.Akhtar, N.Barnes, and A.Mian. (2023). \u201cA Comprehensive Overview of Large Language Models\u201d. arXiv preprintarXiv:2307.06435. URL: https:\/\/arxiv.org\/abs\/2307.06435."},{"key":"2026032901025983900_ref051","unstructured":"OpenAI\n          . (2024). \u201cOpenAI Codex\u201d. URL: https:\/\/openai.com\/index\/openai-codex\/."},{"key":"2026032901025983900_ref052","doi-asserted-by":"publisher","first-page":"822","DOI":"10.1109\/ICCAD.2004.1382689","article-title":"Simultaneous escape routing and layer assignment for dense PCBs","author":"Ozdal","year":"2004"},{"key":"2026032901025983900_ref053","unstructured":"Primis AI\n          . (2025). \u201cPrimis AI: Welcome to the Future of Hardware Design\u201d. URL: https:\/\/primis.ai\/."},{"key":"2026032901025983900_ref054","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-71713-5","volume-title":"Low Power Design Essentials","author":"Rabaey","year":"2009"},{"key":"2026032901025983900_ref055","first-page":"363","article-title":"Security challenges in hardware used for smart environments","author":"Rajendran","year":"2020"},{"key":"2026032901025983900_ref056","doi-asserted-by":"publisher","first-page":"69603","DOI":"10.1109\/ACCESS.2024.3400685","article-title":"Trustworthy Integrated Circuits: From Safety to Security and Beyond","volume":"12","author":"Rama","year":"2024","journal-title":"IEEE Access"},{"issue":"10","key":"2026032901025983900_ref057","doi-asserted-by":"publisher","first-page":"3162","DOI":"10.1109\/TCAD.2021.3124762","article-title":"MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper","volume":"41","author":"Rapp","year":"2022","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"2026032901025983900_ref058","volume-title":"System-on-a-chip Verification: Methodology and Techniques","author":"Rashinkar","year":"2007"},{"issue":"0","key":"2026032901025983900_ref059","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1080\/09747338.2024.2311372","article-title":"Chiplets for Integration of Electronic Systems","volume":"0","author":"Ravikumar","year":"2024","journal-title":"IETE Journal of Education"},{"issue":"2","key":"2026032901025983900_ref060","doi-asserted-by":"crossref","first-page":"76","DOI":"10.1109\/MDAT.2016.2526612","article-title":"The changing computing paradigm with internet of things: A tutorial introduction","volume":"33","author":"Ray","year":"2016","journal-title":"IEEE Design & Test"},{"issue":"2","key":"2026032901025983900_ref061","doi-asserted-by":"publisher","first-page":"121","DOI":"10.1561\/1000000022","article-title":"Power Modeling and Characterization of Computing Devices","volume":"6","author":"Reda","year":"2012","journal-title":"Foundations and Trends\u00ae in Electronic Design Automation"},{"key":"2026032901025983900_ref062","first-page":"63","article-title":"Top level SOC interconnectivity verification using formal techniques","author":"Roy","year":"2007"},{"key":"2026032901025983900_ref063","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/ACCESS.2024.3427369","article-title":"LLM for SoC Security: A Paradigm Shift","volume-title":"IEEE Access","author":"Saha","year":"2024"},{"key":"2026032901025983900_ref064","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-01875-7","volume-title":"Power Estimation on Electronic System Level Using Linear Power Models","author":"Schuermans","year":"2019"},{"key":"2026032901025983900_ref065","first-page":"356","article-title":"Sciduction: Combining induction, deduction, and structure for verification and synthesis","author":"Seshia","year":"2012"},{"key":"2026032901025983900_ref066","doi-asserted-by":"publisher","DOI":"10.1145\/3670474.3685960","article-title":"OpenROAD-Assistant: An Open-Source Large Language Model for Physical Design Tasks","author":"Sharma","year":"2024"},{"key":"2026032901025983900_ref067","unstructured":"Siemens\n          . (2023). \u201cA New Era of EDA Powered by AI\u201d. URL: https:\/\/resources.sw.siemens.com\/en-US\/white-paper-a-new-era-of-eda-powered-by-AI."},{"key":"2026032901025983900_ref068","unstructured":"Silimate, Inc.\n           (2025). \u201cSilimate: Streamlining Chip Design Workflows\u201d. URL: %7Bhttps:\/\/www.silimate.com\/%7D."},{"key":"2026032901025983900_ref069","first-page":"168","article-title":"Transaction flows and executable models: Formalization and analysis of message-passing protocols","author":"Talupur","year":"2015"},{"key":"2026032901025983900_ref070","first-page":"37","article-title":"Integrating AI and Machine Learning with UVM in Semiconductor Design","volume":"2","author":"Vaithianathan","year":"2024","journal-title":"ESP International journal of Advancements in Computational Technology (ESP-IJACT) Volume"},{"key":"2026032901025983900_ref071","first-page":"5998","article-title":"Attention is all you need","author":"Vaswani","year":"2017"},{"key":"2026032901025983900_ref072","doi-asserted-by":"crossref","first-page":"27","DOI":"10.54254\/2755-2721\/92\/20241685","article-title":"Enhancing chip design verification through AI-powered bug detection in RTL code","volume":"92","author":"Wang","year":"2024","journal-title":"Applied and Computational Engineering"},{"key":"2026032901025983900_ref073","doi-asserted-by":"publisher","first-page":"385","DOI":"10.1109\/ISVLSI61997.2024.00076","article-title":"LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust","author":"Wang","year":"2024"},{"key":"2026032901025983900_ref074","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/LAD62341.2024.10691774","article-title":"EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD","author":"Wu","year":"2024"},{"issue":"10","key":"2026032901025983900_ref075","doi-asserted-by":"publisher","first-page":"3184","DOI":"10.1109\/TCAD.2024.3383347","article-title":"ChatEDA: A Large Language Model Powered Autonomous Agent for EDA","volume":"43","author":"Wu","year":"2024","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"2","key":"2026032901025983900_ref076","doi-asserted-by":"publisher","first-page":"285","DOI":"10.1109\/TCAD.2011.2169258","article-title":"Correctly Modeling the Diagonal Capacity in Escape Routing","volume":"31","author":"Yan","year":"2012","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"2026032901025983900_ref077","doi-asserted-by":"publisher","first-page":"581586","DOI":"10.1109\/ICCAD.1995.480175","article-title":"Single-layer fanout routing and routability analysis for ball grid arrays","author":"Yu","year":"1995"},{"key":"2026032901025983900_ref078","article-title":"A Survey of Large Language Models","volume-title":"arXiv preprint","author":"Zhao","year":"2023"},{"key":"2026032901025983900_ref079","unstructured":"Zhong, R., X.Du, S.Kai, Z.Tang, S.Xu, H.-L.Zhen, J.Hao, Q.Xu, M.Yuan, and J.Yan. (2023). \u201cLLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation\u201d. URL: https:\/\/arxiv.org\/abs\/2401.12224."}],"container-title":["Foundations and Trends\u00ae in Electronic Design Automation"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.emerald.com\/fteda\/article-pdf\/14\/4\/245\/10995738\/1000000063-1en.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/www.emerald.com\/fteda\/article-pdf\/14\/4\/245\/10995738\/1000000063-1en.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,4,29]],"date-time":"2026-04-29T14:13:39Z","timestamp":1777472019000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.emerald.com\/fteda\/article\/14\/4\/245\/1324717\/Deep-Learning-and-Generative-AI-for-Monolithic-and"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,1,5]]},"references-count":79,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2025,1,5]]}},"URL":"https:\/\/doi.org\/10.1561\/1000000063-1","relation":{},"ISSN":["1551-3939","1551-3947"],"issn-type":[{"value":"1551-3939","type":"print"},{"value":"1551-3947","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,1,5]]}}}