{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,29]],"date-time":"2022-03-29T01:58:57Z","timestamp":1648519137697},"reference-count":10,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"5","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2013]]},"DOI":"10.1587\/elex.10.20120902","type":"journal-article","created":{"date-parts":[[2013,3,6]],"date-time":"2013-03-06T07:37:45Z","timestamp":1362555465000},"page":"20120902-20120902","source":"Crossref","is-referenced-by-count":0,"title":["An all-digital PLL with supply insensitive digitally controlled oscillator"],"prefix":"10.1587","volume":"10","author":[{"given":"Seong-Young","family":"Seo","sequence":"first","affiliation":[{"name":"College of Information and Communication Engineering, Sungkyunkwan Univesity"},{"name":"Memory Division, Samsung Electronics Co."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jung-Hoon","family":"Chun","sequence":"additional","affiliation":[{"name":"College of Information and Communication Engineering, Sungkyunkwan Univesity"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Young-Hyun","family":"Jun","sequence":"additional","affiliation":[{"name":"Memory Division, Samsung Electronics Co."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kee-Won","family":"Kwon","sequence":"additional","affiliation":[{"name":"College of Information and Communication Engineering, Sungkyunkwan Univesity"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] J. Li, N. Ning, L. Du, Q. Yu, and Y. Liu, &ldquo;The Impact of Gate Leakage Current on PLL in 65nm Technology: Analysis and Optimization,&rdquo; <i>J. Semiconductor Technology and Science<\/i><i>,<\/i> vol. 12, no. 1, pp. 99-106, March 2012.","DOI":"10.5573\/JSTS.2012.12.1.99"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] R. B. Staszewski and P. T. Balsara, &ldquo;Phase-Domain All-Digital Phase-Locked Loop,&rdquo; <i>IEEE Trans. Circuits Syst. II, Exp. Briefs<\/i>, vol. 52, no. 3, pp. 159-163, March 2005.","DOI":"10.1109\/TCSII.2004.842067"},{"key":"3","unstructured":"[3] L. Xu, S. Lindfors, K. Stadius, and J. Ryyn&auml;nen, &ldquo;A 2.4-GHz Low-Power All-Digital Phase-Locked Loop,&rdquo; <i>IEEE J. Solid-State Circuits<\/i><i>,<\/i> vol. 45, no. 8, pp. 1513-1521, Aug. 2010."},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] E. Temporiti, C. Weltin-Wu, and F. Svelto, &ldquo;A 3GHz Fractional All-Digital PLL with a 1.8MHz Bandwidth Implementing Spur Reduction Techniques,&rdquo; <i>IEEE J. Solid-State Circuits<\/i><i>,<\/i> vol. 44, no. 3, pp. 824-834, July 2009.","DOI":"10.1109\/JSSC.2008.2012363"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] V. Kratyuk, P. K. Hanumolu, U.-K. Moon, and K. Mayaram, &ldquo;A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy,&rdquo; <i>IEEE Trans. Circuits Syst. II, Exp. Briefs<\/i>, vol. 54, no. 3, pp. 247-251, March 2007.","DOI":"10.1109\/TCSII.2006.889443"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] S.-Y. Seo, J.-H. Chun, Y.-H. Jun, S. Kim, and K.-W. Kwon, &ldquo;A Digitally Controlled Oscillator with Wide Frequency Range and Low Supply Sensitivity,&rdquo; <i>IEEE Trans. Circuits Syst. II, Exp. Briefs<\/i>, vol. 58, no. 10, pp. 632-636, Oct. 2011.","DOI":"10.1109\/TCSII.2011.2164146"},{"key":"7","unstructured":"[7] R. B. Staszewski, C. Hung, N. Barton, M. Lee, and F. Svelto, &ldquo;A Digitally Controlled Oscillator in a 90nm Digital CMOS Process for Mobile Phones,&rdquo; <i>IEEE J. Solid-State Circuits<\/i><i>,<\/i> vol. 40, no. 11, pp. 2203-2211, Nov. 2005."},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] R. B. Stasewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, &ldquo;1.3V 20ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS,&rdquo; <i>IEEE Trans. Circuits Syst. II, Exp. Briefs<\/i>, vol. 53, no. 3, pp. 220-224, March 2006.","DOI":"10.1109\/TCSII.2005.858754"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] I.-C. Hwang, C.-W. Kim, and S.-M. Kang, &ldquo;A CMOS Self-Regulating VCO with Low Supply Sensitivity,&rdquo; <i>IEEE J. Solid-State Circuits<\/i>, vol. 39, no. 1, pp. 42-48, Jan. 2004.","DOI":"10.1109\/JSSC.2003.820881"},{"key":"10","unstructured":"[10] B.-M. Moon, Y.-J. Park, and D.-K. Jeong, &ldquo;Monotonic Wide-Range Digitally Controlled Oscillator Compensated for Supply Voltage Variation,&rdquo; <i>IEEE Trans. Circuits Syst. II, Exp. Briefs<\/i>, vol. 55, no. 10, pp. 1036-1040, Oct. 2008."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/10\/5\/10_10.20120902\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,23]],"date-time":"2021-04-23T16:20:30Z","timestamp":1619194830000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/10\/5\/10_10.20120902\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"references-count":10,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2013]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.10.20120902","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013]]}}}