{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,30]],"date-time":"2026-03-30T12:12:50Z","timestamp":1774872770226,"version":"3.50.1"},"reference-count":15,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2013]]},"DOI":"10.1587\/elex.10.20130404","type":"journal-article","created":{"date-parts":[[2013,6,11]],"date-time":"2013-06-11T23:08:28Z","timestamp":1370992108000},"page":"20130404-20130404","source":"Crossref","is-referenced-by-count":18,"title":["Hamming network circuits based on CMOS\/memristor hybrid design"],"prefix":"10.1587","volume":"10","author":[{"given":"Xuan","family":"Zhu","sequence":"first","affiliation":[{"name":"State Key Laboratory of High Performance Computing, National University of Defense Technology"},{"name":"School of Computer, National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xuejun","family":"Yang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of High Performance Computing, National University of Defense Technology"},{"name":"School of Computer, National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chunqing","family":"Wu","sequence":"additional","affiliation":[{"name":"School of Computer, National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Junjie","family":"Wu","sequence":"additional","affiliation":[{"name":"State Key Laboratory of High Performance Computing, National University of Defense Technology"},{"name":"School of Computer, National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xun","family":"Yi","sequence":"additional","affiliation":[{"name":"State Key Laboratory of High Performance Computing, National University of Defense Technology"},{"name":"School of Computer, National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] J. Misra and I. Saha: Neurocomputing <b>74<\/b> [1-3] (2010) 239.","DOI":"10.1016\/j.neucom.2010.03.021"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] O. Temam: ACM SIGARCH Computer Architecture News <b>38<\/b> [3] (2010) 349.","DOI":"10.1145\/1816038.1816008"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] D. Strukov, G. Snider, D. Stewart and R. Williams: Nature <b>453<\/b> [7191] (2008) 80.","DOI":"10.1038\/nature06932"},{"key":"4","unstructured":"[4] G. Snider: Proc. 2008 International Symposium on Nanoscale Architecture (2008) 85."},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] S. Jo, T. Chang, I. Ebong, B. Bhadviya, P. Mazumder and W. Lu: Nano Letters <b>10<\/b> [4] (2010) 1297.","DOI":"10.1021\/nl904092h"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] Y. Chen, G. Jung, D. Ohlberg, X. Li, D. Stewart, J. Jeppesen, K. Nielsen, J. Stoddart and R. Williams: Nanotechnology <b>14<\/b> (2003) 462.","DOI":"10.1088\/0957-4484\/14\/4\/311"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] K. Kim, S. Gaba, D. Wheeler, J. M. Cruz-Albrecht, T. Hussain, N. Srinivasa and W. Lu: Nano Letters <b>12<\/b> [1] (2012) 389.","DOI":"10.1021\/nl203687n"},{"key":"8","unstructured":"[8] M. Hagan, H. Demuth and M. Beale: <i>Neural network design<\/i> (PWS, Boston, 1996)."},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] I. E. Ebong and P. Mazumder: IEEE Trans. Nanotechnol. <b>10<\/b> [6] (2011) 1454.","DOI":"10.1109\/TNANO.2011.2166805"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] X. Zhu, C. Wu, Y. Tang, J. Wu and X. Yi: IEICE Electron. Express <b>10<\/b> [5] (2013) 1.","DOI":"10.1587\/elex.10.20130013"},{"key":"11","unstructured":"[11] J. Lazzaro, S. Ryckebusch, M. Mahowald and C. Mead: <i>Advances in neural information processing systems<\/i> <b>1<\/b> (Morgan Kaufman Publishers, 1989) 703."},{"key":"12","unstructured":"[12] A. Fish and O. Yadid-Pecht: The 2001 IEEE International Symposium on Circuits and Systems <b>3<\/b> (2001) 636."},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] C. Yakopcic, T. M. Taha, G. Subramanyam, R. E. Pino and S. Roger: IEEE Electron Device Lett. <b>32<\/b> [10] (2011) 1436.","DOI":"10.1109\/LED.2011.2163292"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] Y. He, U. Cilingiroglu and E. Sanchez-Sinencio: IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>1<\/b> [1] (1993) 56.","DOI":"10.1109\/92.219907"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] M. Robinson, H. Yoneda and E. Sanchez-Sinencio: IEEE Trans. Neural Netw. <b>3<\/b> [3] (1992) 444.","DOI":"10.1109\/72.129417"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/10\/12\/10_10.20130404\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,23]],"date-time":"2021-04-23T17:45:54Z","timestamp":1619199954000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/10\/12\/10_10.20130404\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"references-count":15,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2013]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.10.20130404","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013]]}}}