{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,2]],"date-time":"2025-05-02T04:13:07Z","timestamp":1746159187188,"version":"3.40.4"},"reference-count":9,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"3","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2014]]},"DOI":"10.1587\/elex.11.20140011","type":"journal-article","created":{"date-parts":[[2014,1,23]],"date-time":"2014-01-23T23:51:15Z","timestamp":1390521075000},"page":"20140011-20140011","source":"Crossref","is-referenced-by-count":0,"title":["Mitigation of process variation effect in FPGAs with partial rerouting method"],"prefix":"10.1587","volume":"11","author":[{"given":"Zhenyu","family":"Guan","sequence":"first","affiliation":[{"name":"Department of Electrical and Electronic, Imperial College London, South Kensington Campus"}]},{"given":"Justin S. J.","family":"Wong","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic, Imperial College London, South Kensington Campus"}]},{"given":"Sumanta","family":"Chaudhuri","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic, Imperial College London, South Kensington Campus"}]},{"given":"George","family":"Constantinides","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic, Imperial College London, South Kensington Campus"}]},{"given":"Peter Y. K.","family":"Cheung","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic, Imperial College London, South Kensington Campus"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2121913"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] P. Sedcole and P. Y. K. Cheung: ACM. Reconfigurable Tech. <b>1<\/b> (2008) 1936.","DOI":"10.1145\/1371579.1371582"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] Y. Lin, L. He and M. Hutton: IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>16<\/b> (2008) 124.","DOI":"10.1109\/TVLSI.2007.912027"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] N. Mehta, R. Rubin and A. DeHon: Proc. ACM\/SIGDA International Symposium on Field Programmable Gate Arrays (2012) 97.","DOI":"10.1145\/2145694.2145710"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] J. S. J. Wong, P. Sedcole and P. Y. K. Cheung: International Conference on ICECE Technology (2008) 105.","DOI":"10.1109\/FPT.2008.4762372"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] R. Rubin and A. DeHon: Proc. 19th ACM\/SIGDA International Symposium on Field Programmable Gate Arrays (2011) 173.","DOI":"10.1145\/1950413.1950447"},{"key":"7","unstructured":"[7] Z. Guan, J. S. J. Wong, S. Chaudhuri, G. Constantinides and P. Y. K. Cheung: submitted to IEEE. FPT."},{"key":"8","unstructured":"[8] Z. Guan: Ph.D thesis Imperial College London, Lodnon (2013)."},{"key":"9","unstructured":"[9] International Technology Roadmap for Semiconductors (ITRS): http:\/\/www.itrs.net\/Links\/2012ITRS\/Home2012.htm."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/11\/3\/11_11.20140011\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,1]],"date-time":"2025-05-01T17:00:39Z","timestamp":1746118839000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/11\/3\/11_11.20140011\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014]]},"references-count":9,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2014]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.11.20140011","relation":{},"ISSN":["1349-2543"],"issn-type":[{"type":"electronic","value":"1349-2543"}],"subject":[],"published":{"date-parts":[[2014]]}}}