{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,6,12]],"date-time":"2024-06-12T11:16:35Z","timestamp":1718190995443},"reference-count":13,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"11","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2016]]},"DOI":"10.1587\/elex.13.20160090","type":"journal-article","created":{"date-parts":[[2016,5,23]],"date-time":"2016-05-23T11:37:23Z","timestamp":1464003443000},"page":"20160090-20160090","source":"Crossref","is-referenced-by-count":9,"title":["New adaptable three-moduli set {2&lt;i&gt;&lt;sup&gt;n&lt;\/sup&gt;&lt;\/i&gt;&lt;sup&gt;+&lt;\/sup&gt;&lt;i&gt;&lt;sup&gt;k&lt;\/sup&gt;&lt;\/i&gt;, 2&lt;i&gt;&lt;sup&gt;n&lt;\/sup&gt;&lt;\/i&gt; \u2212 1, 2&lt;i&gt;&lt;sup&gt;n&lt;\/sup&gt;&lt;\/i&gt;&lt;sup&gt;\u22121&lt;\/sup&gt; \u2212 1} for residue number system-based finite impulse response implementation"],"prefix":"10.1587","volume":"13","author":[{"given":"Ming-Hwa","family":"Sheu","sequence":"first","affiliation":[{"name":"Department of Electronic Engineering, National Yunlin University of Science & Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Siang-Min","family":"Siao","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, National Yunlin University of Science & Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yin-Tsung","family":"Hwang","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Chung Hsing University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chi-Chia","family":"Sun","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Formosa University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"You-Ping","family":"Lin","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, National Yunlin University of Science & Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] B. Parhami: <i>Computer Arithmetic: Algorithms and Hardware Designs<\/i> (Oxford University Press, 2010)."},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] R. Conway and J. Nelson: \u201cImproved RNS FIR filter architectures,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>51<\/b> (2004) 26 (DOI: 10.1109\/TCSII.2003.821524).","DOI":"10.1109\/TCSII.2003.821524"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] S. Pontarelliz, <i>et al.<\/i>: \u201cA novel error detection and correction technique for RNS based FIR filters,\u201d IEEE Int. Symp. on Defect and Fault Tolerance of VLSI Syst. (2008) 436 (DOI: 10.1109\/DFT.2008.32).","DOI":"10.1109\/DFT.2008.32"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] Y. Wanget al.: \u201cAdder based residue to binary numbers converters for (2<i><sup>n<\/sup><\/i> \u2212 1, 2<i><sup>n<\/sup><\/i>, 2<i><sup>n<\/sup><\/i> + 1),\u201d IEEE Trans. Signal Process. <b>50<\/b> (2002) 1772 (DOI: 10.1109\/TSP.2002.1011216).","DOI":"10.1109\/TSP.2002.1011216"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] M. H. Sheuet al.: \u201cEfficient reverse converter design for new adaptable four-moduli set {2<i><sup>n<\/sup><\/i><sup>+<\/sup><i><sup>k<\/sup><\/i>, 2<i><sup>n<\/sup><\/i> + 1, 2<i><sup>n<\/sup><\/i> \u2212 1, 2<sup>2<\/sup><i><sup>n<\/sup><\/i> + 1},\u201d IEICE Trans. Fundam. Electron. Commun. Comput. Sci. <b>E96-A<\/b> (2013) 1571 (DOI: 10.1587\/transfun.E96.A.1571).","DOI":"10.1587\/transfun.E96.A.1571"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] R. Chaves and L. Sousa: \u201c{2<i><sup>n<\/sup><\/i> + 1, 2<i><sup>n<\/sup><\/i><sup>+<\/sup><i><sup>k<\/sup><\/i>, 2<i><sup>n<\/sup><\/i> \u2212 1}: a new RNS moduli set extension,\u201d IEEE Euromicro Symp. on Digital Syst. Design (2004) 210 (DOI: 10.1109\/DSD.2004.1333279).","DOI":"10.1109\/DSD.2004.1333279"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] P. Patronik and S. J. Piestrak: \u201cDesign of reverse converters for general RNS moduli sets {2<i><sup>k<\/sup><\/i>, 2<i><sup>n<\/sup><\/i> \u2212 1, 2<i><sup>n<\/sup><\/i> + 1, 2<i><sup>n<\/sup><\/i><sup>+1<\/sup> \u2212 1} and {2<i><sup>k<\/sup><\/i>, 2<i><sup>n<\/sup><\/i> \u2212 1, 2<i><sup>n<\/sup><\/i> + 1, 2<i><sup>n<\/sup><\/i><sup>\u22121<\/sup> \u2212 1} (n even),\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>61<\/b> (2014) 1687 (DOI: 10.1109\/TCSI.2013.2290843).","DOI":"10.1109\/TCSI.2013.2290843"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] R. Zimmermann: \u201cEfficient VLSI implementation of modulo (2<i><sup>n<\/sup><\/i> \u00b1 1) addition and multiplication,\u201d IEEE Symp. on Comput. Arithmetic (1999) 158 (DOI: 10.1109\/ARITH.1999.762841).","DOI":"10.1109\/ARITH.1999.762841"},{"key":"9","unstructured":"[9] A. S. Molahosseiniet al.: \u201cEfficient MRC-based residue to binary converters for the new moduli sets {2<sup>2<\/sup><i><sup>n<\/sup><\/i>, 2<i><sup>n<\/sup><\/i> \u2212 1, 2<i><sup>n<\/sup><\/i><sup>+1<\/sup> \u2212 1} and {2<sup>2<\/sup><i><sup>n<\/sup><\/i>, 2<i><sup>n<\/sup><\/i> \u2212 1, 2<i><sup>n<\/sup><\/i><sup>\u22121<\/sup> \u2212 1},\u201d IEICE Trans. Inf. Syst. <b>E92.D<\/b> (2009) 1628 (DOI: 10.1587\/transinf.E92.D.1628)."},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] A. S. Molahosseiniet al.: \u201cA reduced-area reverse converter for the moduli set {2<i><sup>n<\/sup><\/i>, 2<i><sup>n<\/sup><\/i> \u2212 1, 2<i><sup>2n<\/sup><\/i><sup>\u22121<\/sup> \u2212 1},\u201d Int. J. Adv. Comput. Technol. <b>2<\/b> [5] (2010) 61 (DOI: 10.4156\/ijact.vol2.issue5.6).","DOI":"10.4156\/ijact.vol2.issue5.6"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] K. A. Gbolagade, <i>et al.<\/i>: \u201cAn improved RNS reverse converter for the {2<sup>2<\/sup><i><sup>n<\/sup><\/i><sup>+1<\/sup> \u2212 1, 2<i><sup>n<\/sup><\/i>, 2<i><sup>n<\/sup><\/i> \u2212 1} moduli set,\u201d IEEE Int. Symp. on ISCAS (2010) 2103 (DOI: 10.1109\/ISCAS.2010.5537062).","DOI":"10.1109\/ISCAS.2010.5537062"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] A. B. Premkumaret al.: \u201cImproved memoryless RNS forward converter based on the periodicity of residues,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>53<\/b> (2006) 133.","DOI":"10.1109\/TCSII.2005.857090"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] D. G. Manolakis and V. K. Ingle: <i>Applied Digital Signal Processing<\/i> (Cambridge University Press, 2011).","DOI":"10.1017\/CBO9780511835261"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/13\/11\/13_13.20160090\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,8]],"date-time":"2019-09-08T12:27:43Z","timestamp":1567945663000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/13\/11\/13_13.20160090\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":13,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2016]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.13.20160090","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016]]}}}