{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,27]],"date-time":"2026-05-27T18:39:35Z","timestamp":1779907175289,"version":"3.53.1"},"reference-count":10,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"10","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2016]]},"DOI":"10.1587\/elex.13.20160328","type":"journal-article","created":{"date-parts":[[2016,4,25]],"date-time":"2016-04-25T22:27:35Z","timestamp":1461623255000},"page":"20160328-20160328","source":"Crossref","is-referenced-by-count":11,"title":["Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur"],"prefix":"10.1587","volume":"13","author":[{"given":"Abdul Majeed Kottampara","family":"Kuppalath","sequence":"first","affiliation":[{"name":"Indian Institute of Information Technology Design and Manufacturing (IIITDM)"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Binsu J","family":"Kailath","sequence":"additional","affiliation":[{"name":"Indian Institute of Information Technology Design and Manufacturing (IIITDM)"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] M. Mansuriet al.: IEEE J. Solid-State Circuits <b>37<\/b> (2002) 1331 (DOI: 10.1109\/JSSC.2002.803048).","DOI":"10.1109\/JSSC.2002.803048"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] A. K. K. Majeed and B. J. Kailath: Procedia Eng. <b>64<\/b> (2013) 377 (DOI: 10.1016\/j.proeng.2013.09.110).","DOI":"10.1016\/j.proeng.2013.09.110"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] J. Lan, <i>et al.<\/i>: IEEE ASICON Proc. (2009) 1117.","DOI":"10.1109\/ASICON.2009.5351378"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] L. C. Liu and B. H. Li: Electron. Lett. <b>40<\/b> (2004) 918 (DOI: 10.1049\/el:20045367).","DOI":"10.1049\/el:20045367"},{"key":"5","unstructured":"[5] M. Lin, <i>et al.<\/i>: DTIS in Nanoscale (2007) 124."},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] I. C. Hwang and S. G. Bae: Electron. Lett. <b>45<\/b> (2009) 1273 (DOI: 10.1049\/el.2009.2660).","DOI":"10.1049\/el.2009.2660"},{"key":"7","unstructured":"[7] W. Rhee: IEEE ISCAS Proc. (1999) 545 (DOI: 10.1109\/ISCAS.1999.780807)."},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] K. Wooet al.: IEEE J. Solid-State Circuits <b>43<\/b> (2008) 379 (DOI: 10.1109\/JSSC.2007.914281).","DOI":"10.1109\/JSSC.2007.914281"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] W. S. Changet al.: IEEE J. Solid-State Circuits <b>49<\/b> (2014) 2964 (DOI: 10.1109\/JSSC.2014.2359670).","DOI":"10.1109\/JSSC.2014.2359670"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] C. W. Hsuet al.: IEEE Trans. Circuits Syst. I, Reg. Papers <b>62<\/b> (2015) 90 (DOI: 10.1109\/TCSI.2014.2359719).","DOI":"10.1109\/TCSI.2014.2359719"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/13\/10\/13_13.20160328\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,2]],"date-time":"2025-06-02T21:43:21Z","timestamp":1748900601000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/13\/10\/13_13.20160328\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":10,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2016]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.13.20160328","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016]]}}}