{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,30]],"date-time":"2022-03-30T10:25:16Z","timestamp":1648635916537},"reference-count":18,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"18","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2016]]},"DOI":"10.1587\/elex.13.20160720","type":"journal-article","created":{"date-parts":[[2016,8,30]],"date-time":"2016-08-30T18:08:12Z","timestamp":1472580492000},"page":"20160720-20160720","source":"Crossref","is-referenced-by-count":1,"title":["Additive-calibration scheme for leakage compensation of low voltage SRAM"],"prefix":"10.1587","volume":"13","author":[{"given":"Chunyu","family":"Peng","sequence":"first","affiliation":[{"name":"School of Electronics and Information Engineering, Anhui University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiangwen","family":"An","sequence":"additional","affiliation":[{"name":"School of Electronics and Information Engineering, Anhui University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhiting","family":"Lin","sequence":"additional","affiliation":[{"name":"School of Electronics and Information Engineering, Anhui University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiulong","family":"Wu","sequence":"additional","affiliation":[{"name":"School of Electronics and Information Engineering, Anhui University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei","family":"Hong","sequence":"additional","affiliation":[{"name":"State Grid Anhui Electric Power Research Institute"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] J. A. Fredenburg and M. P. Flynn: \u201cA 90-MS\/s 11-MHz-bandwidth 62-dB SNDR noise-shaping SAR ADC,\u201d IEEE J. Solid-State Circuits <b>47<\/b> (2012) 2898 (DOI: 10.1109\/JSSC.2012.2217874).","DOI":"10.1109\/JSSC.2012.2217874"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] A. T. Doet al.: \u201cSensing margin enhancement techniques for ultra-low-voltage SRAMs utilizing a bitline-boosting current and equalized bitline leakage,\u201d IEEE Trans. Circuits Syst. II <b>59<\/b> (2012) 868 (DOI: 10.1109\/TCSII.2012.2231014).","DOI":"10.1109\/TCSII.2012.2231014"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] B. Wanget al.: \u201cDesign of an ultra-low voltage 9T SRAM with equalized bitline leakage and CAM-assisted energy efficiency improvement,\u201d IEEE Trans. Circuits Syst. I <b>62<\/b> (2015) 441 (DOI: 10.1109\/TCSI.2014.2360760).","DOI":"10.1109\/TCSI.2014.2360760"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] Z. Guan and M. Marek-Sadowska: \u201cIncorporating process variations into SRAM electromigration reliability assessment using atomic flux divergence,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>24<\/b> (2016) 2195 (DOI: 10.1109\/TVLSI.2015.2501900).","DOI":"10.1109\/TVLSI.2015.2501900"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] G. Pasandi and S. M. Fakhraie: \u201cA 256-kb 9T near-threshold SRAM with 1k cells per bitline and enhanced write and read operations,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>23<\/b> (2015) 2438 (DOI: 10.1109\/TVLSI.2014.2377518).","DOI":"10.1109\/TVLSI.2014.2377518"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] F. Moradi, <i>et al.<\/i>: \u201c65NM sub-threshold 11T-SRAM for ultra low voltage applications,\u201d SOCC Dig. Tech. Papers (2008) 113 (DOI: 10.1109\/SOCC.2008.4641491).","DOI":"10.1109\/SOCC.2008.4641491"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] J. Chenet al.: \u201cMaximum - ultra-low voltage circuit design in the presence of variations,\u201d IEEE Circuits Devices Mag. <b>21<\/b> (2005) 12 (DOI: 10.1109\/MCD.2005.1578583).","DOI":"10.1109\/MCD.2005.1578583"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] W. Dehaene, <i>et al.<\/i>: \u201cEmbedded SRAM design in deep deep submicron technologies,\u201d ESSCIRC Dig. Tech. Papers (2007) 384 (DOI: 10.1109\/ESSCIRC.2007.4430324).","DOI":"10.1109\/ESSCIRC.2007.4430324"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] Y. Yeet al.: \u201cA 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bit-line leakage reduction (BLR) technique,\u201d IEEE J. Solid-State Circuits <b>38<\/b> (2003) 839 (DOI: 10.1109\/JSSC.2003.810057).","DOI":"10.1109\/JSSC.2003.810057"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] T.-H. Kimet al.: \u201cA 0.2 V, 480 kb subthreshold SRAM with 1k cells per bitline for ultra-low-voltage computing,\u201d IEEE J. Solid-State Circuits <b>43<\/b> (2008) 518 (DOI: 10.1109\/JSSC.2007.914328).","DOI":"10.1109\/JSSC.2007.914328"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] E. Morifujiet al.: \u201cSupply and threshold-voltage trends for scaled logic and SRAM MOSFETs,\u201d IEEE Trans. Electron Devices <b>53<\/b> (2006) 1427 (DOI: 10.1109\/TED.2006.874752).","DOI":"10.1109\/TED.2006.874752"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] K. Agawaet al.: \u201cA bitline leakage compensation scheme for low-voltage SRAMs,\u201d IEEE J. Solid-State Circuits <b>36<\/b> (2001) 726 (DOI: 10.1109\/4.918909).","DOI":"10.1109\/4.918909"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] Y.-C. Lai and S.-Y. Huang: \u201cX-calibration: A technique for combating excessive bitline leakage current in nanometer SRAM designs,\u201d IEEE J. Solid-State Circuits <b>43<\/b> (2008) 1964 (DOI: 10.1109\/JSSC.2008.2001937).","DOI":"10.1109\/JSSC.2008.2001937"},{"key":"14","doi-asserted-by":"publisher","unstructured":"[14] C.-H. Lo and S.-Y. Huang: \u201cP-P-N based 10T SRAM cell for low-leakage and resilient subthreshold operation,\u201d IEEE J. Solid-State Circuits <b>46<\/b> (2011) 695 (DOI: 10.1109\/JSSC.2010.2102571).","DOI":"10.1109\/JSSC.2010.2102571"},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] Y. Takeyamaet al.: \u201cA low leakage SRAM macro with replica cell biasing scheme,\u201d IEEE J. Solid-State Circuits <b>41<\/b> (2006) 815 (DOI: 10.1109\/JSSC.2006.870763).","DOI":"10.1109\/JSSC.2006.870763"},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] M. Goudarzi and T. Ishihara: \u201cSRAM leakage reduction by row\/column redundancy under random within-die delay variation,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>18<\/b> (2010) 1660 (DOI: 10.1109\/TVLSI.2009.2026048).","DOI":"10.1109\/TVLSI.2009.2026048"},{"key":"17","doi-asserted-by":"publisher","unstructured":"[17] Y. Nikiet al.: \u201cA digitized replica bitline delay technique for random-variation-tolerant timing generation of SRAM sense amplifiers,\u201d IEEE J. Solid-State Circuits <b>46<\/b> (2011) 2545 (DOI: 10.1109\/JSSC.2011.2164294).","DOI":"10.1109\/JSSC.2011.2164294"},{"key":"18","doi-asserted-by":"publisher","unstructured":"[18] B. S. Amrutur and M. A. Horowitz: \u201cA replica technique for wordline and sense control in low-power SRAM\u2019s,\u201d IEEE J. Solid-State Circuits <b>33<\/b> (1998) 1208 (DOI: 10.1109\/4.705359).","DOI":"10.1109\/4.705359"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/13\/18\/13_13.20160720\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,24]],"date-time":"2017-06-24T17:40:33Z","timestamp":1498326033000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/13\/18\/13_13.20160720\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":18,"journal-issue":{"issue":"18","published-print":{"date-parts":[[2016]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.13.20160720","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016]]}}}