{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,30]],"date-time":"2022-03-30T11:05:08Z","timestamp":1648638308805},"reference-count":12,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"20","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2016]]},"DOI":"10.1587\/elex.13.20160806","type":"journal-article","created":{"date-parts":[[2016,10,6]],"date-time":"2016-10-06T22:10:05Z","timestamp":1475791805000},"page":"20160806-20160806","source":"Crossref","is-referenced-by-count":0,"title":["Design of local ESD clamp for cross-power-domain interface circuits"],"prefix":"10.1587","volume":"13","author":[{"given":"Chun-Yu","family":"Lin","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, National Taiwan Normal University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu-Kai","family":"Chiu","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Taiwan Normal University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shuan-Yu","family":"Yueh","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Taiwan Normal University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] ESDA\/JEDEC Joint Standard JS-001-2014."},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] C. Duvvuryet al.: \u201cInternal chip ESD phenomena beyond the protection circuit,\u201d IEEE Trans. Electron Devices <b>35<\/b> (1988) 2133 (DOI: 10.1109\/16.8787).","DOI":"10.1109\/16.8787"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] Y. Koo and K. Lee: \u201cSCR-based ESD protection device with low trigger and high robustness for I\/O clamp,\u201d IEICE Electron. Express <b>9<\/b> (2012) 200 (DOI: 10.1587\/elex.9.200).","DOI":"10.1587\/elex.9.200"},{"key":"4","unstructured":"[4] G. Notermans, <i>et al.<\/i>: \u201cGate oxide protection and ggNMOSTs in 65 nm,\u201d Proc. EOS\/ESD Symp. (2008) 6."},{"key":"5","unstructured":"[5] N. Kitagawa, <i>et al.<\/i>: \u201cAn active ESD protection technique for the power domain boundary in a deep submicron IC,\u201d Proc. EOS\/ESD Symp. (2006) 196."},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] S.-H. Chenet al.: \u201cActive ESD protection design for interface circuits between separated power domains against cross-power-domain ESD stresses,\u201d IEEE Trans. Device Mater. Rel. <b>8<\/b> (2008) 549 (DOI: 10.1109\/TDMR.2008.2002492).","DOI":"10.1109\/TDMR.2008.2002492"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] S.-H. Chenet al.: \u201cLocal CDM ESD protection circuits for cross-power domains in 3D IC applications,\u201d IEEE Trans. Device Mater. Rel. <b>14<\/b> (2014) 781 (DOI: 10.1109\/TDMR.2014.2320538).","DOI":"10.1109\/TDMR.2014.2320538"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] J. Chun and C. Chen: \u201cLeakage power reduction using the body bias and pin reordering technique,\u201d IEICE Electron. Express <b>13<\/b> (2016) 20151052 (DOI: 10.1587\/elex.13.20151052).","DOI":"10.1587\/elex.13.20151052"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] C.-T. Wang and M.-D. Ker: \u201cDesign of 2\u00d7VDD-tolerant power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm CMOS technology,\u201d IEEE Trans. Electron Devices <b>57<\/b> (2010) 1460 (DOI: 10.1109\/TED.2010.2046457).","DOI":"10.1109\/TED.2010.2046457"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] M.-D. Ker and P.-Y. Chiu: \u201cNew low-leakage power-rail ESD clamp circuit in a 65-nm low-voltage CMOS process,\u201d IEEE Trans. Device Mater. Rel. <b>11<\/b> (2011) 474 (DOI: 10.1109\/TDMR.2010.2066976).","DOI":"10.1109\/TDMR.2010.2066976"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] F. Maet al.: \u201cInvestigation of boundary-MOS-triggered SCR structures for on-chip ESD protection,\u201d Electron. Lett. <b>47<\/b> (2011) 246 (DOI: 10.1049\/el.2010.3524).","DOI":"10.1049\/el.2010.3524"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] M.-D. Ker and S.-H. Chen: \u201cImplementation of initial-on ESD protection concept with PMOS-triggered SCR devices in deep-submicron CMOS technology,\u201d IEEE J. Solid-State Circuits <b>42<\/b> (2007) 1158 (DOI: 10.1109\/JSSC.2007.894823).","DOI":"10.1109\/JSSC.2007.894823"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/13\/20\/13_13.20160806\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,10,29]],"date-time":"2016-10-29T03:08:50Z","timestamp":1477710530000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/13\/20\/13_13.20160806\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":12,"journal-issue":{"issue":"20","published-print":{"date-parts":[[2016]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.13.20160806","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016]]}}}