{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,11]],"date-time":"2025-06-11T23:40:02Z","timestamp":1749685202612,"version":"3.41.0"},"reference-count":11,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"22","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2016]]},"DOI":"10.1587\/elex.13.20160903","type":"journal-article","created":{"date-parts":[[2016,11,1]],"date-time":"2016-11-01T22:08:27Z","timestamp":1478038107000},"page":"20160903-20160903","source":"Crossref","is-referenced-by-count":4,"title":["A high-precision hardware-efficient radix-2&lt;sup&gt;k&lt;\/sup&gt; FFT processor for SAR imaging system"],"prefix":"10.1587","volume":"13","author":[{"given":"Chen","family":"Yang","sequence":"first","affiliation":[{"name":"Beijing Key Laboratory of Embedded Real-time Information Processing Technology, Beijing Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yizhuang","family":"Xie","sequence":"additional","affiliation":[{"name":"Beijing Key Laboratory of Embedded Real-time Information Processing Technology, Beijing Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"He","family":"Chen","sequence":"additional","affiliation":[{"name":"Beijing Key Laboratory of Embedded Real-time Information Processing Technology, Beijing Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cuimei","family":"Ma","sequence":"additional","affiliation":[{"name":"Institute of Electronics, Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] C. H. Yanget al.: \u201cPower and area minimization of reconfigurable FFT processors: A 3GPP-LTE example,\u201d IEEE J. Solid-State Circuits <b>47<\/b> (2012) 757 (DOI: 10.1109\/JSSC.2011.2176163).","DOI":"10.1109\/JSSC.2011.2176163"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] S. Li, <i>et al.<\/i>: \u201cA 128\/256-point pipeline FFT\/IFFT processor for MIMO OFDM system IEEE 802.16e,\u201d IEEE International Symposium on Circuits and Systems (2010) 1488 (DOI: 10.1109\/ISCAS.2010.5537355).","DOI":"10.1109\/ISCAS.2010.5537355"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] Y. Chenet al.: \u201cAn indexed-scaling pipelined FFT processor for OFDM-based WPAN applications,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>55<\/b> (2008) 146 (DOI: 10.1109\/TCSII.2007.910771).","DOI":"10.1109\/TCSII.2007.910771"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] A. Corteset al.: \u201cRadix-r<sup>k<\/sup>, FFTs: Matricial representation and SDC\/SDF pipeline implementation,\u201d IEEE Trans. Signal Process. <b>57<\/b> (2009) 2824 (DOI: 10.1109\/TSP.2009.2016276).","DOI":"10.1109\/TSP.2009.2016276"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] M. Garridoet al.: \u201cPipelined radix-2<sup>k<\/sup> feedforward FFT architectures,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>21<\/b> (2013) 23 (DOI: 10.1109\/TVLSI.2011.2178275).","DOI":"10.1109\/TVLSI.2011.2178275"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] C. Yang, <i>et al.<\/i>: \u201cNew quantization error assessment methodology for fixed-point pipeline FFT processor design,\u201d IEEE International System-on-Chip Conference (SOCC) (2014) 299 (DOI: 10.1109\/SOCC.2014.6948944).","DOI":"10.1109\/SOCC.2014.6948944"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] C. Ma, <i>et al.<\/i>: \u201cSimplified addressing scheme for mixed radix FFT algorithms,\u201d IEEE Conf. Acoustics, Speech, Signal Prog (ICASSP) (2014) 8355 (DOI: 10.1109\/ICASSP.2014.6855231).","DOI":"10.1109\/ICASSP.2014.6855231"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] Y. Xieet al.: \u201cOn finite word length computing error of fixed-point SAR imaging processing,\u201d Chin. J. Electron. (2014) 645.","DOI":"10.23919\/CJE.2014.10851225"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] A. V. Oppenheim and C. J. Weinstein: \u201cEffects of finite register length in digital filtering and the fast Fourier transform,\u201d Proc. IEEE <b>60<\/b> (1972) 957 (DOI: 10.1109\/PROC.1972.8820).","DOI":"10.1109\/PROC.1972.8820"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] S. He and M. Torkelson: \u201cDesign and implementation of a 1024-point pipeline FFT processor,\u201d Custom Integrated Circuits Conference (1998). 346 (DOI: 10.1109\/CICC.1998.694922).","DOI":"10.1109\/CICC.1998.694922"},{"key":"11","unstructured":"[11] P. R. Panda: \u201cSystemC: A modeling platform supporting multiple design abstractions,\u201d International Symposium on System Synthesis (2001) 75 (DOI: 10.1109\/ISSS.2001.156535)."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/13\/22\/13_13.20160903\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,11]],"date-time":"2025-06-11T23:11:04Z","timestamp":1749683464000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/13\/22\/13_13.20160903\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":11,"journal-issue":{"issue":"22","published-print":{"date-parts":[[2016]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.13.20160903","relation":{},"ISSN":["1349-2543"],"issn-type":[{"type":"electronic","value":"1349-2543"}],"subject":[],"published":{"date-parts":[[2016]]}}}