{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,4]],"date-time":"2022-04-04T13:03:38Z","timestamp":1649077418104},"reference-count":16,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"23","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2016]]},"DOI":"10.1587\/elex.13.20161000","type":"journal-article","created":{"date-parts":[[2016,11,16]],"date-time":"2016-11-16T22:06:35Z","timestamp":1479333995000},"page":"20161000-20161000","source":"Crossref","is-referenced-by-count":0,"title":["State synchronization technique based on present input and healthy state for repairable TMR systems"],"prefix":"10.1587","volume":"13","author":[{"given":"Rui","family":"Yao","sequence":"first","affiliation":[{"name":"College of Automation and Engineering, Nanjing University of Aeronautics and Astronautics"}]},{"given":"Jun","family":"Wu","sequence":"additional","affiliation":[{"name":"Beijing Institute of Control Engineering"}]},{"given":"Meiqun","family":"Wang","sequence":"additional","affiliation":[{"name":"College of Automation and Engineering, Nanjing University of Aeronautics and Astronautics"}]},{"given":"Xueyan","family":"Zhong","sequence":"additional","affiliation":[{"name":"Nanjing Institute of Railway Technology"}]},{"given":"Ping","family":"Zhu","sequence":"additional","affiliation":[{"name":"College of Automation and Engineering, Nanjing University of Aeronautics and Astronautics"}]},{"given":"Jiemei","family":"Liang","sequence":"additional","affiliation":[{"name":"Beijing Institute of Control Engineering"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] Z. Yanget al.: \u201cA new automatic method for testing interconnect resources in FPGAs based on general routing matrix,\u201d IEICE Electron. Express <b>12<\/b> (2015) 20150747 (DOI: 10.1587\/elex.12.20150747).","DOI":"10.1587\/elex.12.20150747"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] M. Ebrahimiet al.: \u201cLow cost scan-chain-based technique to recover multiple errors in TMR systems,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>21<\/b> (2013) 1454 (DOI: 10.1109\/TVLSI.2012.2213102).","DOI":"10.1109\/TVLSI.2012.2213102"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] K. S. Morganet al.: \u201cA comparison of TMR with alternative fault-tolerant design techniques for FPGAs,\u201d IEEE Trans. Nucl. Sci. <b>54<\/b> (2007) 2065 (DOI: 10.1109\/TNS.2007.910871).","DOI":"10.1109\/TNS.2007.910871"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] S. Y. Yu and E. J. McCluskey: \u201cOn-line testing and recovery in TMR systems for real-time applications,\u201d ITC Dig. Tech. Papers (2001) 240 (DOI: 10.1109\/TEST.2001.966639).","DOI":"10.1109\/TEST.2001.966639"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] J. Losq: \u201cA highly efficient redundancy scheme: self-purging redundancy,\u201d IEEE Trans. Comput. <b>C-25<\/b> (1976) 569 (DOI: 10.1109\/TC.1976.1674656).","DOI":"10.1109\/TC.1976.1674656"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] H. Asadi and M. B. Tahoori: \u201cAnalytical techniques for soft error rate modeling and mitigation of FPGA-based designs,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>15<\/b> (2007) 1320 (DOI: 10.1109\/TVLSI.2007.909795).","DOI":"10.1109\/TVLSI.2007.909795"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] S. J. Adams: \u201cHardware assisted recovery from transient errors in redundant processing systems,\u201d FTCS-19 Dig. Tech. Papers (1989) 512 (DOI: 10.1109\/FTCS.1989.105628).","DOI":"10.1109\/FTCS.1989.105628"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] M. Berget al.: \u201cEffectiveness of internal versus external SEU scrubbing mitigation strategies in a Xilinx FPGA,\u201d IEEE Trans. Nucl. Sci. <b>55<\/b> (2008) 2259 (DOI: 10.1109\/TNS.2008.2001422).","DOI":"10.1109\/TNS.2008.2001422"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] J. Tonfat, <i>et al.<\/i>: \u201cEnergy efficient frame-level redundancy scrubbing technique for SRAM-based FPGAs,\u201d AHS (2015) 1 (DOI: 10.1109\/AHS.2015.7231160).","DOI":"10.1109\/AHS.2015.7231160"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] N. Imran and R. F. Demara: \u201cA self-configuring TMR scheme utilizing discrepancy resolution,\u201d ReConFig (2011) 398 (DOI: 10.1109\/ReConFig.2011.5).","DOI":"10.1109\/ReConFig.2011.5"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] D. K. Pradhan and N. H. Vaidya: \u201cRoll-forward and rollback recovery: performance-reliability trade-off,\u201d IEEE Trans. Comput. <b>46<\/b> (1997) 372 (DOI: 10.1109\/12.580435).","DOI":"10.1109\/12.580435"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] J. Xu and B. Randell: \u201cRoll-forward error recovery in embedded real-time systems,\u201d ICPADS (1996) 414 (DOI: 10.1109\/ICPADS.1996.517589).","DOI":"10.1109\/ICPADS.1996.517589"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] M. Ebrahimi, <i>et al.<\/i>: \u201cScTMR: a scan chain-based error recovery technique for TMR systems in safety-critical applications,\u201d DATE (2011) 1 (DOI: 10.1109\/DATE.2011.5763277).","DOI":"10.1109\/DATE.2011.5763277"},{"key":"14","doi-asserted-by":"publisher","unstructured":"[14] R. Al-Haddad, <i>et al.<\/i>: \u201cSustainable modular adaptive redundancy technique emphasizing partial reconfiguration for reduced power consumption,\u201d Int. J. Reconfigurable Comput. (2011) 2011 (DOI: 10.1155\/2011\/430808).","DOI":"10.1155\/2011\/430808"},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] R. Yaoet al.: \u201cMulti-objective evolutionary design of selective triple modular redundancy systems against SEUs,\u201d Chin. J. Aeronauti. <b>28<\/b> (2015) 804 (DOI: 10.1016\/J.CJA.2015.03.005).","DOI":"10.1016\/j.cja.2015.03.005"},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] X. Huanget al.: \u201cAn evolutionary algorithm based on novel hybrid repair strategy for combinational logic circuit,\u201d IEICE Electron. Express <b>12<\/b> (2015) 20150765 (DOI: 10.1587\/ELEX.12.20150765).","DOI":"10.1587\/elex.12.20150765"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/13\/23\/13_13.20161000\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,25]],"date-time":"2017-06-25T03:44:14Z","timestamp":1498362254000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/13\/23\/13_13.20161000\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":16,"journal-issue":{"issue":"23","published-print":{"date-parts":[[2016]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.13.20161000","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016]]}}}