{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T07:22:52Z","timestamp":1773818572352,"version":"3.50.1"},"reference-count":14,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"1","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/elex.13.20161134","type":"journal-article","created":{"date-parts":[[2016,12,15]],"date-time":"2016-12-15T23:02:00Z","timestamp":1481842920000},"page":"20161134-20161134","source":"Crossref","is-referenced-by-count":33,"title":["An efficient implementation of 2D convolution in CNN"],"prefix":"10.1587","volume":"14","author":[{"given":"Jing","family":"Chang","sequence":"first","affiliation":[{"name":"School of Electrical Science and Engineering, Nanjing University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jin","family":"Sha","sequence":"additional","affiliation":[{"name":"School of Electrical Science and Engineering, Nanjing University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] C. Farabet, <i>et al.<\/i>: \u201cCNP: An FPGA-based processor for convolutional networks,\u201d FPL (2009) 32 (DOI: 10.1109\/FPL.2009.5272559).","DOI":"10.1109\/FPL.2009.5272559"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] C. Garcia and M. Delakis: \u201cConvolutional face finder: A neural architecture for fast and robust face detection,\u201d IEEE Trans. Pattern Anal. Mach. Intell. <b>26<\/b> (2004) 1408 (DOI: 10.1109\/TPAMI.2004.97).","DOI":"10.1109\/TPAMI.2004.97"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] M. Ranzato, <i>et al.<\/i>: \u201cUnsupervised learning of invariant feature hierarchies with applications to object recognition,\u201d CVPR (2007) (DOI: 10.1109\/CVPR.2007.383157).","DOI":"10.1109\/CVPR.2007.383157"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] M. Sankaradas, <i>et al.<\/i>: \u201cA massively parallel coprocessor for convolutional neural networks,\u201d ASAP (2009) 53 (DOI: 10.1109\/ASAP.2009.25).","DOI":"10.1109\/ASAP.2009.25"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] S. Chakradharet al.: \u201cA dynamically configurable coprocessor for convolutional neural networks,\u201d ACM SIGARCH Computer Architecture News <b>38<\/b> (2010) 247 (DOI: 10.1145\/1815961.1815993).","DOI":"10.1145\/1815961.1815993"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] T. Chenet al.: \u201cA small-footprint high-throughput accelerator for ubiquitous machine-learning,\u201d SIGPLAN Not. <b>49<\/b> (2014) 269 (DOI: 10.1145\/2541940.2541967).","DOI":"10.1145\/2541940.2541967"},{"key":"7","unstructured":"[7] A. Krizhevsky, <i>et al.<\/i>: \u201cImagenet classification with deep convolutional neural networks,\u201d Advances in Neural Information Processing Systems 25 (2012) 1097."},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] J. Cong and B. Xiao: \u201cMinimizing computation in convolutional neural networks,\u201d Artificial Neural Networks and Machine Learning-ICANN (2014) 281.","DOI":"10.1007\/978-3-319-11179-7_36"},{"key":"9","unstructured":"[9] C. Zhang, <i>et al.<\/i>: \u201cOptimizing FPGA-based accelerator design for deep convolutional neural networks,\u201d ACM\/SIGDA FPGA (2015) 161 (DOI: 10.1145\/2684746.2689060)."},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] N. Li, <i>et al.<\/i>: \u201cA multistage dataflow implementation of a deep convolutional neural network based on FPGA for high-speed object recognition,\u201d SSIAI (2016) 165 (DOI: 10.1109\/SSIAI.2016.7459201).","DOI":"10.1109\/SSIAI.2016.7459201"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] H. Nakahara and T. Sasao: \u201cA deep convolutional neural network based on nested residue number system,\u201d FPL (2015) 1 (DOI: 10.1109\/FPL.2015.7293933).","DOI":"10.1109\/FPL.2015.7293933"},{"key":"12","unstructured":"[12] R. G. Shoup: \u201cParameterized convolution filtering in a field programmable gate array,\u201d Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs (1994) 274."},{"key":"13","unstructured":"[13] GitHub DeepLearnToolbox: https:\/\/github.com\/rasmusbergpalm\/DeepLearnToolbox\/blob\/master\/tests\/test_example_CNN.m."},{"key":"14","unstructured":"[14] Google Code Project Hosting: https:\/\/code.google.com\/p\/cuda-convnet\/."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/1\/14_13.20161134\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,16]],"date-time":"2019-09-16T16:14:42Z","timestamp":1568650482000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/14\/1\/14_13.20161134\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":14,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.13.20161134","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]}}}